搜索资源列表
suij
- 硬件编程实现伪随机交织器和随机交织器,应用环境Quartus II5.0-hardware programming pseudo-random interleaver and random interleaver, application environment Quartus II5.0
QuartusII_sum
- Altera Quartus II使用方法的总结性文件-Altera Quartus II use of the concluding document
quartusGuide
- 设计输入 ! 多种设计输入方法 – Quartus II • 原理图式图形设计输入 • 文本编辑 – AHDL, VHDL, Verilog • 内存编辑 – Hex, Mif – 第三方工具 • EDIF • HDL • VQM – 或采用一些别的方法去优化和提高输入的灵活性: • 混合设计格式 •
Quartus_vhdl
- 用QUARTUS编译通过的等精度频率计,我错误,但有几个警告(不影响设计)。我的毕业设计啊!!! -QUARTUS used by the compiler, and other precision frequency, I am wrong. But there are several warning (not affect design). I graduated from the design ah! ! !
b8bit_adder
- 8位的加法器设计,分4个工程完成的,用的是Quartus II软件。-eight of the adder design, four hours to complete the project, using the Quartus II software.
shuzilvboqideyingjianshixian
- 数字滤波器的硬件实现,里面实例可以直接在quartus中运行-Digital Filter hardware, which can be directly examples run in quartus
IIS_VHDL
- VHDL实现了IIS接口程序,在Quartus II 6.0上编译通过,在板子上可以读取IIS数据-IIS VHDL interface procedures, the Quartus II 6.0 compiled by the board can read data IIS
GuangShanChi
- 光栅尺的四细分和辩向电路,并具有计数器功能,利用Quartus综合,可以参考-Grating four segments and the dialectic to the circuit, and have counter functions, using Quartus integrated, can refer to
leon3-altera-ep2s60-ddr
- This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be r
SignalTapII
- Altera公司Quartus II软件的逻辑分析使用流程,中文版本。该文件详细说明了使用SingalTapII的流程和基本使用方法,对使用FPGA的人有很大帮助。
srbjq
- quartus环境下开发的三人表决器(三种不同的描述方式)maxplusII兼容
intro_to_quartus2_chinese
- 本手册针对的读者是 Quartus II 软件的初学者,它概述了可编程逻辑设计中 Quartus II 软件的功能。
Crack_QII71_b156
- Quartus v7.1的key_gen b156破解器-The Quartus v7.1 crack key_gen b156 browser
fft_IPcore
- 这是一个fft的IP核,安装要求为quartus6.0以上。解压安装后可在quartus里例化使用,元件主要为cyclone和stratix,最大支持1024点的转换。
QuartusII_lab
- Quartus II的实验指导。对初学QUQARTUS II 的业内人士适用-Quartus II experimental guidance. For beginner QUQARTUS II applies to the industry
qqq
- 数字滤波器的vhdl源代码.在quartus上运行过,里面还有matlab的仿真文件.-Digital filter of the VHDL source code. In Quartus run-off, along with the simulation matlab file.
sd_audio_aic23
- SD卡和AIC23数字音频输出实验, FreeDev Audio Dsp Board采用了TI公司的TVL320AIC23 1、控制接口使用I2C,Quartus中将CS置低(器件地址0011010)。 2、数字音频接口使用了组件FreeDev_aic23,有三种测试和应用 模式,中断结合DMA方式能在NIOS II中采集和发送数据。中断信号 产生于模块中FIFO缓冲区的半满信号,读取数据端口自动清除中断 请求信号。 3
Freq
- 简易数字频率计,用Verilog HDL编写的,基于Quartus II实现,结构清晰,功能较为全面,能满足简单的频率测量要求-Simple digital frequency meter, using Verilog HDL prepared, based on the Quartus II realize, clear structure, function is more comprehensive to meet the sim
quartusfft
- Quartus MegaCore FFT usage. Incluging example.
altera_ram
- 本程序对如何使用altera系列芯片片上ram进行实例演示,采用Verilog HDL语言编写,并使用modelsim与quartus联合进行功能仿真。本原码是红色逻辑开发板的试验程序,值得一看。-This procedure of how to use the altera series chip-chip ram for example demonstration, using Verilog HDL language, and u