文件名称:leon3-altera-ep2s60-ddr
介绍说明－－下载内容均来自于网络，请自行研究使用
This leon3 design is tailored to the Altera NiosII Startix2
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM.
As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written.
NOTE: the test bench cannot be simulated with DDR enabled
because the Altera pads do not have the correct delay models.
* How to program the flash prom with a FPGA programming file
1. Create a hex file of the programming file with Quartus.
2. Convert it to srecord and adjust the load address:
objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec
3. Program the flash memory using grmon:
flash erase 0x800000 0xb00000
flash load fpga.srec-This leon3 design is tailored to the Altera NiosII Startix2
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM.
As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written.
NOTE: the test bench cannot be simulated with DDR enabled
because the Altera pads do not have the correct delay models.
* How to program the flash prom with a FPGA programming file
1. Create a hex file of the programming file with Quartus.
2. Convert it to srecord and adjust the load address:
objcopy--adjust-vma=0x800000 output_file.hexout-O srec fpga.srec
3. Program the flash memory using grmon:
flash erase 0x800000 0xb00000
flash load fpga.srec
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM.
As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written.
NOTE: the test bench cannot be simulated with DDR enabled
because the Altera pads do not have the correct delay models.
* How to program the flash prom with a FPGA programming file
1. Create a hex file of the programming file with Quartus.
2. Convert it to srecord and adjust the load address:
objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec
3. Program the flash memory using grmon:
flash erase 0x800000 0xb00000
flash load fpga.srec-This leon3 design is tailored to the Altera NiosII Startix2
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM.
As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written.
NOTE: the test bench cannot be simulated with DDR enabled
because the Altera pads do not have the correct delay models.
* How to program the flash prom with a FPGA programming file
1. Create a hex file of the programming file with Quartus.
2. Convert it to srecord and adjust the load address:
objcopy--adjust-vma=0x800000 output_file.hexout-O srec fpga.srec
3. Program the flash memory using grmon:
flash erase 0x800000 0xb00000
flash load fpga.srec
(系统自动生成,下载前可以参看下载内容)
下载文件列表
leon3-altera-ep2s60-ddr
.......................\.config
.......................\ahbrom.vhd
.......................\config.help
.......................\config.in
.......................\config.vhd
.......................\config.vhd.h
.......................\config.vhd.in
.......................\config_test.h
.......................\defconfig
.......................\indata
.......................\lconfig.tk
.......................\leon3mp.vhd
.......................\linkprom
.......................\Makefile
.......................\output_file.cof
.......................\prom.h
.......................\prom.srec
.......................\README.txt
.......................\sdram.srec
.......................\smc_mctrl.vhd
.......................\sram.srec
.......................\systest.c
.......................\testbench.vhd
.......................\tkconfig.h
.......................\wave.do
.......................\.config
.......................\ahbrom.vhd
.......................\config.help
.......................\config.in
.......................\config.vhd
.......................\config.vhd.h
.......................\config.vhd.in
.......................\config_test.h
.......................\defconfig
.......................\indata
.......................\lconfig.tk
.......................\leon3mp.vhd
.......................\linkprom
.......................\Makefile
.......................\output_file.cof
.......................\prom.h
.......................\prom.srec
.......................\README.txt
.......................\sdram.srec
.......................\smc_mctrl.vhd
.......................\sram.srec
.......................\systest.c
.......................\testbench.vhd
.......................\tkconfig.h
.......................\wave.do