搜索资源列表
DE2_NIOS_LITE_SRAM
- DE2-SRAM-IP-CORE 需要开发ip core的朋友可以参考哦 ~-DE2-SRAM-IP-CORE need to develop friends can ip core reference Oh ~
EP2C-SOURCE_CODE
- 有關於EP2C的一些程序(EX:I2C,FLASH,IRDA,MUSIC,LED,LIGHT,SRAM,UART,PS2,SPI )-EP2C on some of the procedures (EX: I2C, FLASH, IRDA, MUSIC, LED, LIGHT, SRAM, UART, PS2, SPI)
sram
- LF2407A上的外扩SRAM芯片的调试程序,需要CCS软件开发平台-LF2407A on foreign expansion SRAM chip debugger, the need for CCS Software Development Platform
CY7c68013_fpga_write_sram
- FPGA自FX2 slavefifo中读取数据,写入至SRAM-FPGA since FX2 slavefifo read data, write to the SRAM
PLD_SRAM
- PLD自增读写SRAM,有好的参照作用,希望大家指点和帮助。-PLD by reading and writing since the SRAM, has reference to the role of good, I hope everyone pointing and help.
LM3SLib_GPIO_Parallel-Bus
- LM3S系列ARM用GPIO模拟并行总线扩展32KB SRAM PF0~PF7 D0~D7(数据总线) PA0~PA7 A0~A7(地址总线低8位) PB0~PB7 A8~A15(地址总线高8位) PB7 /CE(片选) PC4 /WE(写使能) PC5 /OE(读使能) 32KB SRAM 映射在地址0x0000~0x4FFF之间 为了加快访问速度,软件上将采用寄存器方式进行操作 PB7
altera_up_avalon_sram
- 基于Avalon的SDRAM控制器IP核-Avalon SRAM Controller
123
- sram读模块基于FPGA的实现 verilog源代码-sram
sram_controller
- sram 控制器的三种实现方案,来自xinlix工程师之手,不可多得-sram controller implementation of the three programs, from the hands of engineers xinlix, rare
sram
- ccs下用来测试davinci板子的led模块的工程-ccs under davinci board used to test the led module works
STC_2uart-sram
- 双串口收发多串口收发,单片机间的通信,实现很多的功能-Dual serial multi-transceiver serial port transceiver, single-chip communication to achieve a lot of features
niossramflash
- 在altera FPGA ep3c25器件上实现niosii+sram+flash-Altera FPGA ep3c25 in devices to achieve niosii+ sram+ flash
niossram
- altera fpga ep3c25器件微处理器开发,niosii+sram, 已编译通过,可直接下载到开发板-altera fpga ep3c25 the development of microprocessor devices, niosii+ sram, compiled through, can be directly downloaded to the development board
AVR
- avrC语言 全局和局部变量 • 全局变量 – 在 startup 初始化 – 存储于 SRAM – 必须加载到寄存器堆中 • 局部变量 – 在函数初期初始化 – 存储于寄存器当中直至函数结束-awqvrCyuyan] 全局和局部变量 • 全局变量 – 在 startup 初始化 – 存储于 SRAM – 必须加载到寄存器堆中 • 局部变
FGPA-SRAM-Programe
- FPGA编程方法介绍,方便学习VHDL,公供大家参考-fpga programe medoth, study hardware vhdl language
sram216
- SRAM IS61LVC12824,读写控制程序,用CPLD 95216设计-SRAM IS61LVC12824, read and write control procedures, with the design of CPLD 95216
use_SRAM_design_FIFO.pdf
- 利用sram技术设计的一个FIFO-failed to translate
EP1C3_12_5_RSV
- 基于FPGA的数字存储示波器,用VHDL实现的,压缩包里是Quartus工程。AD采样送进FPGA,存入SRAM后用DA在普通示波器上可以显示。-FPGA-based digital storage oscilloscope, using VHDL achieved compression is Quartus project bag. AD sample into FPGA, after SRAM into DA in ordinar
interleaver
- This is a convolutional interleaver code written in verilog, the ram is sram with ram_ncs, ram_nwe, ram_noe characters.
Protecting_FPGA
- How to protect your FPGA design (IP) on SRAM based FPGA s against copying.