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uvm-1.0p1.tar
- Cadence 公司推出的高级验证语言，验证方法学开源-Cadence s introduction of an advanced verification languages, verification methodology open source
Frames
- An example of usage of fr a mes, in visual basic in Spanish for UVM Mexico
Tarea
- Basic Exercises in Java with made with Net Beans 7.3.1 Program for Computer Systems class at the University UVM.
uvm_use_pipelined_ahb
- 一个简单的uvm搭建的ahb简单实例,包含了各个组件以及编译的运行的脚本-one sample example about ahb，include every component and compile scr ipt
uvm_switch_8
- 使用uvm验证环境搭建的testbench，主要验证switch的功能。可以学习uvm的简单功能-use uvm set up testbench ,the mainly focuse is verification swtich,you can learning uvm sample fucntion
Desarrollo-de-Habilidades
- Skills Development regarding iCarnegie ssd1 to what the systems engineering career in uvm. files are listed for the years and come with their respective document prepared in c + +.
UVM_TEST
- UVM 的 入门实例，一个完整的能够跑通的实例。其中包括DUT代码，Testbench代码，还有搭建过程说明。很适合用来学习UVM入门。-This paper describes an approach to using Accellera s UVM, the Universal Verification Methodology, for functional verification by
uvm_switch_8
- 一个非常好的uvm入门例子，编译运行环境为VCS，在linux下直接输入make就可心运行。-uvm simple example
Uvm_mem_example
- uvm example about memory
MastersThesisPreliminaryReport
- developmentof a reconfigurable muti-protocol verification environment using uvm methodology
UVM_Guidlines
- UVM Coding Guidelines for verification
umv_demo
- UVM实践指南的第一章的例程代码 在win7 modelsim SE 10.0c完美运行。。。。。欢迎下载测试，有疑问联系我-The first chapter of the routine practice guidelines UVM code runs perfectly in win7 modelsim SE 10.0c. . . . . Welcome to download the test, have questions,
UVM_Class_Reference_Manual_1.2
- UVM 1.2 类参考手册，UVM验证必备-UVM 1.2 class reference manual
SHIFT-RESISTER.tar
- its about a shift register design using verilog and verification using system verilog files for uvm.
uvm_lab_switch
- 利用最新的UVM验证方法学搭建完整的ASIC的验证平台。-UVM and svtb for ASIC verification
UvmTutorial
- It is a nice UVM tutorial.
Comprehensive-UVMOVM-Acceleration
- Comprehensive UVM/OVM Acceleration
UVM_Golden_Reference_Guide
- The UVM Golden Reference Guide is a compact reference guide to the Universal Verification Methodology for SystemVerilog. it offers answers to the questions most often asked during the practical application of UVM i
uvm_exp
- uvm验证平台简单环境搭建，来自于书《uvm1.1应用指南及源代码分析》，但书中代码无法直接运行，需要进行部分修改。-a simple uvm env
uvm_users_guide_1.2
- UVM验证方法学官方的文档 uvm_users_guide_1.2-uvm users guide 1.2