搜索资源列表
FIFO-Verification-Environment-_-Ayutam-Solutions_
- this the verification environment for fifo using uvm-this is the verification environment for fifo using uvm
UVM_learning
- UVM使用指南和代码分析，有PDF学习指南文档，还有hello入门级代码供参考-UVM guides and code analysis, study guide in PDF documents, as well as entry-level code for reference hello
UVM_Class_Reference_Manual_1.2
- The UVM Class Library provides the building blocks needed to quickly develop wellconstructed and reusable verification components and test environments in SystemVerilog. This UVM Class Reference provides detailed ref
eetop.cn_Uvm_spi_bl_reg_tb
- uvm apb verification env
uvm_axi-master
- axi uvm vip, verification model -axi system verilog
uvm_users_guide_1.2
- uvm验证方法学用户参考手册或指导，非常有用，对IC验证工程师来说，UVM方法学是非常重要的- 46/5000 Uvm yànzhèng fāngfǎ xué yònghù cānkǎo shǒucè huò zhǐdǎo, fēicháng yǒuyòng, duì IC yànzhèng gōngchéngshī lái shuō,UVM fāngfǎ xué shì fēicháng zhòngyào de Uvm V
code_test
- uvm testbench 例子，可以在questa软件里运行，运用shell脚本，在cygwin环境中执行，非常方便-Uvm testbench example, you can run in questa software, the use of shell scr ipt, in cygwin environment, very convenient
uart2bus_testbench_latest.tar
- uart2bus_testbench,uart测试平台，主要运用uvm验证方法学，对uart接口、systemverilog和uvm等ic开发和验证有一个初步了解和掌握。-Uart2bus_testbench, uart test platform, the main use of uvm validation methodology, uart interface, systemverilog and uvm ic developme
Universal_Verification_Methodology
- The universal verification Methodlology is a complete mothodology that codifies the best practices for efficient and exhaustive verification.
Universal_Verification_Methodology_examples
- a practical guide to adopting the universal verification methodology examples The universal verification Methodlology is a complete mothodology that codifies the best practices for efficient and exhaustive verification.
crc7
- 以crc7为例进行UVM的验证 Part 1： 搭建环境。 本文使用的Quartus II 13.1（64 bit），器件库MAX V。写了一个Verilog的简单的crc7。 仿真环境是ModelSim 10.2c。虽说自带UVM库。但是，没找到Modelsim自带的uvm_dpi.dll，于是，还重新编译了一番。 本文在win 10下。下载uvm-1.1d（现在最新版本有1.2d了），放好。(crc7 code by sy
verilab_dvcon2012_uvm_cooper
- Getting Started with UVM by Verilab
uvm-tutorial-for-candy-lovers-master
- 张强书所带代码和PDF,代码验证可用,好好学习(Zhang Qiangshu's code and PDF)
FIFO_UVM
- fifo uvm this is total fifo tb with uvm including score board with total uvm_topology with test cases with rtl giving proper output(this is total fifo tb with uvm including score board with total uvm_topology with t
AHB5-master
- amba ahb2 协议vip，包括master和slave(AMBA AHB 2.0 VIP in SystemVerilog UVM)