搜索资源列表
autoring
- 用VHDL编的一个实用自动打铃系统，EDA课设的一个经典题目源程序-VHDL a series of practical automatic bell system, EDA of a class-based source classic title
FIRvhdl
- 用vhdl实现一个fir滤波器 设计要求： 1．最小阻带衰减-30db。 2．带内波动小于1db． 3．用MATLIB与MAXPLUS2联合设计与仿真-use VHDL to achieve a fir filter design requirements : 1. The smallest stop band attenuation- 30dB. 2. With fluctuating within less than
交通灯_XIN
- 使用vhdl语言编写的交通灯控制程序，带有完整的实验报告。-use of the VHDL language traffic lights control procedures, with a complete report of the experiment.
等精度频率计
- 使用vhdl语言写的fpga的应用程序，使献策内容为等精度频率计-use of the VHDL language they simply write the application procedures so that such ideas as to accuracy Cymometer
20051113104111170
- FPGA的VHDL设计经验总结《小型微型计算机系统》2003年7月-FPGA VHDL design experience, "small micro-computer system," July 2003
uart_verilog
- verilog & vhdl以及外国公司的应用说明。-Verilog
alu_inverter
- 4bit ALU 利用vhdl语言编写的4位ALU 开发环境是在windows下-Band ALU using VHDL language prepared by the four ALU is a development environment under Windows
Altera的IP源码8237
- 名鼎鼎的Synopsys公司出的8051IP Core VHDL语言编写，能被keilC51支持-renowned name of the company Synopsys 8051IP Core VHDL language, support can be keilC51
66_FIR
- 这是一个VHDL写的FIR模块，我的编译环境是QuartusII 5.0-This is a VHDL modules written FIR, I compiler environment is Quartus II 5.0
用VHDL实现布斯算法
- 这个例子是讲述用VHDL实现布斯算法，应该有点用，是我的研究生师哥给我的。-this case is about the use of VHDL Booth algorithm, should use a bit of my graduate students Shige to me.
Sparc_leon_VHDL
- 一个航天航空用的Sparc处理器（配美国欧洲宇航局用的R_tems嵌入式操作系统）的VHDL源代码，但不能保证版图设计ASIC成功 -the Sparc processor (fitted with the United States of the European Space Agency R_tems Embedded operating system) VHDL source code, but it can not guar
8051inVHDL
- 一个8051的VHDL代码，可完整编译， 但不保证版图映射成功，可作为设计微处理器的参考-a 8051 VHDL code can be compiled integrity, but it does not guarantee success territory mapping, the microprocessor can be used as a reference design
VHDL_100Examples
- 北京里工大学ASIC设计研究所的100个 VHDL程序设计例子-Beijing University Institute of ASIC design hundred examples of VHDL Design
tbcpu8bit2
- 极小的CPU的VHDL源代码，仅需要占用32个宏单元的CPLD。除了VHDL源代码还包括了汇编器的C源代码-minimal CPU VHDL source code, only occupy 32 macrocell CPLD. Apart from VHDL source code also includes a compilation of C source code
conv_code
- 用VHDL实现卷积码编码，该码为（2.1.3）型卷积码。-using VHDL Convolutional coding, the code (2.1.3)- Convolutional Codes.
89_full_adder
- 这个是带先行进位的加法器的vhdl代码,比较复杂,仅仅供大家参考.-into first place with the addition of VHDL code more complicated, just for reference.
1.6运算器部件实验：乘法器
- 这个是用vhdl编写的乘法器,仅仅供大家参考-VHDL prepared by the multiplier, just for reference
1.7运算器部件实验：除法器
- 这个是用vhdl语言编写的除法器,仅仅供大家参考.-the VHDL language is used to prepare for the division, just for reference.
booth_mul
- 一种可以完成16位有符号／无符号二进制数乘法的乘法器。该乘法器采用了改进的Booth算法，简化了部分积的符号扩展，采用Wallace树和超前进位加法器来进一步提高电路的运算速度。本乘法器可以作为嵌入式CPU内核的乘法单元，整个设计用VHDL语言实现。-a 16 to be completed with symbols/unsigned multiplication of the number of binary multipliers.
加法
- 测试向量波形产生：VHDL实例---加法器源程序 -test vector Waveform Generator : VHDL example-- Adder source