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trircd-release-5[1].0.9-r.tar.rar
- TR-IRCD is an ircd and a collection of services programs for IRC networks. The ircd is heavily influenced by ircd-hybrid and Bahamut. It includes support for IRC extensions such as md5-encrypted hostnames, local channels
CRC Press Wireless Sensor Networks Architectures A
- CRC Press Wireless Sensor Networks Architectures And Protocols電子書-Wireless Sensor Networks, Architectures and Protocols And e-books
三人表决器
- Three-input Majority Voter -- The entity declaration is followed by three alternative architectures which achieve the same functionality in different ways. -Three-input Majority Voter -- The entity declaration is f
ZVector
- This module provides classes to support Java like component architectures. Its function is designed to be familiar and similar to Java classes,but is not designed to be identical in usage or behavior. This is due to sp
uisp-20050207.tar
- Micro In-System Programmer Brief Installation Notes Enter the src directory. If uisp does not compile successfully, add switch -DNO_DIRECT_IO in the Makefile to remove support for direct I/O port access (that
BoothMultiplier
- -- Booth Multiplier -- This file contains all the entity-architectures for a complete -- k-bit x k-bit Booth multiplier. -- the design makes use of the new shift operators available in the VHDL-93 std -- this des
CRC Press Wireless Sensor Networks Architectures A
- CRC Press Wireless Sensor Networks Architectures And Protocols電子書-Wireless Sensor Networks, Architectures and Protocols And e-books
VLSI__TEST
- 中科院研究生院VLSI测试课程课件，VLSI TEST PRINCIPLES AND ARCHITECTURES Design for Testability，搞好测试必看。-Chinese Academy of Sciences, Graduate School of VLSI test Courseware, VLSI TEST PRINCIPLES AND ARCHITECTURESDesign for Testability
VLSI
- VLSI Test Principles and Architectures Design for Testability..... very nice pdf
Async_fifo_Vijay_A._Nebhrajani
- Asynchronous FIFO Architectures - Designing a FIFO is one of the most common problems an ASIC designer comes across. This series of articles (by a popular author)is aimed at looking at how FIFOs may be designed -- a
T2376
- The main objective of the project was to address the above mentioned trends and to form a consistent concept of an All-IP telecommunications network with wireless access. The project took into account both the user&#
VOLUME-1.-Algorithms-and-Architectures
- VOLUME 1. Algorithms and Architectures
Network-Processors--Architectures--Protocols-and-
- Network processing units (NPUs) will be the occasion of sweeping changes in the network hardware industry over the next few years. This new breed of microchip impacts chip designers like Intel, equipment vendors like Cis
64-ia-32-architectures-software-developer-vol-1-m
- The latest revision of intel 64/32 CPU architectures software developer vol1 manual
Mixed-Architectures
- Mixed Architectures.zip
Learning Deep Architectures for AI
- 一本关于深度架构学习算法，尤其是用来构造更深层模型的非监督学习的单层模型。(Theoretical results suggest that in order to learn the kind of com- plicated functions that can represent high-level abstractions (e.g., in vision, language, and other AI-level tas
Asynchronous FIFO Architectures
- 老外的经典异步FIFO结构讲解，一共三个部分。(Asynchronous FIFO Architectures Vijay A. Nebhrajani)
FPGA-Based Channel Coding Architectures for 5G Wireless
- FPGA-Based Channel Coding Architectures for 5G Wireless 英文论文 对FPGA开发的小伙伴们有点参考作用
IA-32 Architectures Software Developer’s Manual
- Instruction Set Reference, A-Z The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C & 2D: Instruction Set Reference (order numbers 253666, 253667, 326018 and 334569) are part of a set
OpenVPX-Architectures-for-High-Performance-Embedded-Computing
- OpenVPX Architectures for High Performance Embedded Computing