搜索资源列表
asyn_fifo
- verilog编写的异步fifo源代码，asyn_fifo.v为顶层，调用其他四个文件-asynchronous fifo prepared Verilog source code, asyn_fifo.v for top-level, call the other four documents
asyn_FIFO
- 该文档是学习异步FIFO 的参考文档，有需要的可以参考一下。-This document is an asynchronous FIFO to study the reference documents, there is a need that can be reference.
SRAM_controller_of_FPGA
- 视频处理源码，使用pdf格式输出，用的时候自解压，然后拷贝黏贴就行了。-`timescale 1ns/1ns module asyn_fifo(clk_wr,wr_en,clk_rd,rd_en,rst,din,full,empty,dout) input clk_wr,wr_en,clk_rd,rd_en,rst input[7:0] din output full,empty output[7:0] do
AsynFIFO
- Verilog 代码 异步FIFO，可综合，综合效率高，cumming的经典方法。-Verilog code for asynchronous FIFO, Cumming s the classic method.
asyn_fifo
- 本文同步FIFO为TPRAM（两端口RAM，一读一写）。有详细verilog 程序以及说明-FIFO divided by clock domain can be divided into synchronous and asynchronous FIFO FIFO, FIFO read and write only one clock synchronous, asynchronous FIFO read and write
asyn_fifo
- verilog asyn_fifo,内含详细说明,同步FIFO为TPRAM-asyn_fifo include detailed instruction，Synchronous FIFO for TPRAM
asyn_FIFO-
- A asynchronous FIFO is implemented. VHDL fil+ vsim.do scr ipt
asyn_fifo
- 该源码包是异步fifo的Verilog语言模型，主要包括2个部分：异步fifo控制模块、测试文件。(The source package is asynchronous FIFO Verilog language model, including 2 main parts: asynchronous FIFO control module, test files.)
asyn_fifo
- 异步fifo,异步的先进先出，verliog hdl代码，已经经过调试(Asynchronous fifo, asynchronous first out, verliog HDL code, has been debugged)