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RS2322
- verilog 功能：DSP或单片机向FPGA的DPRAM中写入一块数据（最大不超过2K字节,前2个字节为代发送数据长度），然后给出启动信号send_start，本模块自动读出DPRAM中的数据，按设定的波特率将DPRAM中规定的长度的数据发送出去。 接口信号说明： send_start：启动FPGA串行发送脉冲 sys_rst：系统复位脉冲 bps_setup：波特率选择 clk5_714：5.714MHz时钟
pipei
- 匹配字段 非常好用的小程序基于ISE的DPRAM进行并行和串行的数据格式转换-Very easy to match the field program based on ISE' s DPRAM parallel and serial data format conversion
DPram
- read or write control of dual port memory
asyn_fifo
- 本文同步FIFO为TPRAM（两端口RAM，一读一写）。有详细verilog 程序以及说明-FIFO divided by clock domain can be divided into synchronous and asynchronous FIFO FIFO, FIFO read and write only one clock synchronous, asynchronous FIFO read and write
DPram
- read or write control of dual port memory
softing_fw
- low level DPRAM command for Linux v2.13.6.
softing_fw
- low level DPRAM command. Make sure that card->dpram[DPRAM_FCT_HOST] is preset.
dpram
- vhdl code dual port map
video_center_scan_scaler_alpha_blend
- 本工程实现两路视频信号阿尔法通道混合(alpha blend), 视频信号黑点中心 点扫描定位，期间用到视频帧缓存（fr a me cache）、视频信号缩放(scaler)等，且用到ram、DDR2等作为缓存，是很值得参考的视频图像处理工程。-scaler,alpha blend,ddr2 controller,center scan, fr a me cache, dpram, etc by verilog, includ
true_dpram_sclk
- developping dpram app under linux
ECP2M50_PRBS_SERDES_DEMO
- DPRAM is used for one sequence of preamble data and 7-bit PRBS data is followed by the preamble and repeats. G8B10B mode is used. Reference Clock source is Y2(on board oscillator(100MHz)).-DPRAM is used for one sequen
基于Actel-FPGA-的双端口RAM-设计
- 基于Actel-FPGA-的双端口RAM-设计(Base Actel-FPGA-Dual Port Ram design)