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A New Phase-Locked Loop (PLL) System
- An enhanced phase-locked loop (PLL) system is presented and its properties and performance characteristics are investigated. Advantages of the proposed PLL structure over the conventional PLLs including its capability
Phase Locked Loop.mdl
- Phase Locked Loop model for matlab
PhaseLockedLoop
- ％The phase locked loop(PLL),adjusts the phase of a local oscillator ％w.r.t the incoming modulated signal.In this way,the phase of the ％incoming signal is locked and the signal is demodulated.This scheme ％is used
PLL
- 几个锁相环仿真程序－通信技术－不记得哪来的啦。希望有用……。-Several phase-locked loop simulation program- communication technologies- do not remember you come from. Seek to help ... ....
DigitalPLL
- 一篇简单易懂的关于数字锁相环概念原理设计的经典文章-An easy-to-read digital phase-locked loop on the concept of the classic principles of design article
matlab
- pll锁相环仿真程序，经过测试，并附上仿真图，值得学习-pll phase locked loop simulation program, tested with the simulation map, it is worth learning
dpll
- 数字锁相环，采用costas环的数字形式，实现跟踪载波相位，-Digital phase-locked loop, using the digital form costas loop to achieve carrier phase tracking,
pll
- 该程序实现的锁相环，运行环境为matlab，二阶的环路滤波器-The program realization of phase-locked loop, operating environment for matlab, the second-order loop filter
dpll_fpga
- 基于FPGA设计数字锁相环，提出了一种由微分超前/滞后型检相器构成数字锁相环的Verilog-HDL建模方案-FPGA-based design of digital phase-locked loop, a by the differential ahead of/lag type seizure constitutes a digital phase-locked loop phase of the Verilog-HDL mode
MC145152
- 1、数字锁相环的单片机代码。 2、单片机与数字锁相环MC145152的应用系统的设计与实现。-1, the single-chip digital phase-locked loop code. 2, microcontroller and digital PLL MC145152 Application System Design and Implementation.
phase-locked
- 主要是关于锁相环的环路滤波设计与计算，非常经典的-Mainly on the phase-locked loop filter design and calculation, very classic
pll
- 模拟锁相环（apll）的一些simulink模型-Analog phase-locked loop (apll) some simulink model
Phase_Locked_Loop
- Very good code for Phase locked Loop in matlab
PLL
- 锁相环问题的仿真，可以解决数字锁相环的仿真问题-Phase-locked loop simulation problem, can solve the problem of digital phase-locked loop simulation
PhaseLockedLoop
- This tutorial starts with a simple conceptual model of an analog Phase-Locked Loop (PLL). Through elaboration it ends at a model of an all digital and fixed-point phase-locked loop. The final model can serve a starting p
SUOXIANG222
- 锁相环的MATLAB SIMULINK编程，可以供研究锁相环的人员使用-MATLAB SIMULINK programming the phase-locked loop, you can study for the use of Phase-Locked Loop
pll_ok
- 完整的锁相环matlab代码实现，其中包括高斯噪声干扰，频差，相差，给出最后频率及相位收敛结果图。重要的是代码中有本人详细注释，易于理解-Complete phase-locked loop matlab code, including the Gaussian noise interference, frequency difference, a difference, given the final results of the f
verilog
- 采用用verilog语言编写的全数字锁相环的源代码。-Verilog language used by all-digital phase-locked loop' s source code.
Phase Locked Loop2
- 数字锁相环锁定相位一致，调控频率的功能函数(The function function of the locking phase of the digital PLL and the frequency control)
Phase Locked Loop
- 锁相环matlab仿真模拟代码，通过相位实现调控(Phase locked loop matlab simulation code, control by phase)