搜索资源列表
1_TO_4
- 大型risc处理器设计源代码,这是书中的代码 基于流水线的risc cpu设计-large risc processor design source code, which is based on the code book pipelined design of the risc cpu
add_16_pipe
- 16位加法器的流水线计算,verilog代码，用于FPGA平台。-16 pipelined adder, verilog code for the FPGA platform.
CPU_use
- 使用VHDL语言编写的简单8位流水线CPU 它有六级流水功能，通过仿真 可以下载到实验箱，也有波形仿真-use VHDL to prepare a simple eight pipelined CPU it has six functional water, Simulation experiments can be downloaded to the box, a waveform simulation
VLSIASS2
- Self timed pipelined adder
cordic_3
- 流水线结构的cordic，可以输出sin/cos-Pipelined structure cordic, can output sin/cos
pis
- Computer Architecture pipelined implementation simulator-Computer Architecture pipelinedimplementation simulator
mips3
- modelsim+dc开发的4级流水线结构的MIPS CPU，完成基本的逻辑运算和跳转。测试程序为希尔排序，结果正确。-modelsim+ dc development of four pipelined structure MIPS CPU, the completion of the basic logic operations and Jump. Test procedure for the Hill to sort the re
mult_piped_8x8
- 8位乘8位的流水线乘法器，采用Verilog hdl编写-8 x 8-bit pipelined multiplier, used to prepare Verilog hdl
mips_multi
- mips processor multicycle non-pipelined microprocessor by verilog
file_encryption
- AES分组加密算法做的文件加解密演示, 采用多线程流水线方式对文件进行 读->加密/解密->写 操作.-AES block cipher algorithm for encryption and decryption so the paper presentations, the use of multi-threaded pipelined read on paper-> encryption/decryption-
Pipelined_Implementation_of_Baseline_JPEG_Encoder
- Pipelined Implementation of Baseline JPEG Encoder
liushuixian_mul
- 流水线乘法器的VHDL实现，希望对你会有用！-Pipelined multiplier in VHDL implementation, you will want to use!
cordpipe
- pipelined cordic algorithm in hdl
adc
- 1.5-b/s Pipelined A/D behavior model 以及功能包,包括SNR INL DNL测试- 1.5-b/s Pipelined A/D behavior model Include SNR INL DNL test progrems
pipeline_6bADC
- 6bit pipelined adc in matlab
pipeline_10b_adc
- 10bit pipelined adc in matlab
FFT
- 流水线模数转换电路输出信号做fft后求SNR,SNDR的matlab程序-matlab fft program for SNR and SNDR of pipelined analog to digital converter（ADC）
4-10-bit-Pipelined-ADC-Model
- model non linear of 10 bit Pipelined ADC
Pipelined-ADC
- pipelined ADC, 各种参数可调，最后包括fft分析和整个传输曲线-pipelined ADC, adjustable parameters, and finally including the entire transfer curve analysis and fft
SNDR-test-for-pipelined-ADC
- 流水线ADC信噪比测试程序,最后一级flash位数可调，可进行SNDR和SFDR的测试-SNDR test for pipelined ADC