搜索资源列表
RTL8305SB-DEMOBOARD-SCH128P2L-V-2009
- RTL 8305sb demo schematic board fot 5 port switch
RTL-to-Gates-Synthesis-using-Synopsys-Design-Comp
- RTL-to-Gates Synthesis using Synopsys Design Compiler.rar
aes_verilog
- A RTL verilog coding for the project AES, which is a cryptography based concepts
I2C_Verilog_Model
- 该源程序包是I2C的Verilog语言模型，包括以下4个部分：RTL源代码，测试平台，软件仿真代码，说明文件。-This source package is I2C bus model based on Verilog language. It has the following 4 parts: RTL code, testbench, sofeware simulating code, help document.
SD_Controller_Verilog
- 该程序包是SD卡/MMC卡控制器SDC的verilog语言包，它包括以下4部分：RTL源代码，测试平台，软件仿真文件，说明文件。-This source package is the SD card and MMC card controler model based on the Verilog language. It has the following 4 parts: RTL language, testbench, softw
Verilog-Digital-System-Design
- Verilog数字系统设计——RTL综合.测试平台与验证 书中的所有源代码-Verilog Digital System Design- RTL synthesis. Test and verification platform for all the source code for the book
spi_driver_verilog
- SPI控制器RTL级源码，实现标准SPI硬件接口-SPI controller RTL-level source code to achieve the standard SPI hardware interface
interpolation-filer-rtl
- synthesizable verilog rtl implemetation of interpolation filter, for both asic and fpga. 64x interpolation. interp_filter.v interp_first.v interp_second.v interp_third.v upsample.v
Principles-of-Verifiable-RTL-Design
- RTL可验证性设计的经典书籍，由惠普大牛撰写！-RTL the verifiability design classic books written by the Hewlett-Packard, Daniel!
Verilog-digital-system-design-RTL-synthesis-testb
- verilog book. RTL sysnthesis testbech
verification-of-SLM-and-RTL
- VERIFICATION OF SLM AND RTL
rtl.tar
- This RTL of Router by uisng verilog-This is RTL of Router by uisng verilog
rtl
- This is also RTL of router by using another type of method
IEEE-Std-1364.1-2002-Verilog-RTL-Synthesys
- IEEE Std 1364.1-2002 Verilog RTL Synthesys
IEEE-Std-1076.6-1999-VHDL-RTL-Synthesis
- IEEE Std 1076.6-1999 VHDL RTL Synthesis
Principles-of-Verifiable-RTL-Design
- 本书主要以HDL（verilog/vhdl）为例，详细讲述了在IC DESIGN FLOW中 Verification 以及Test的设计思想、方法和技巧，涵概了测试的各个方面， 是目前进行IC设计的同仁们最为推荐的一本宝典-(Kluwer) Principles of Verifiable RTL Design (2nd Ed.)
RTL
- 主要讲述的是发射机和接收机在RTL 仿真的时候，剔除DAC 和ADC 模块 进行无缝连接的模块说明-Focuses on the transmitter and receiver in RTL simulation time, excluding the DAC and ADC module Seamless connection module descr iption
RTL
- UART RTL测试程序，用于串口调试，红色飓风E16开发板使用-UART RTL test procedures for serial debugging
verilog数字系统设计-rtl综合、测试平台与验证源代码
- verilog 程序，verilog数字系统设计-rtl综合、测试平台与验证源代码
RTL-coding-guidelines
- RTL coding guidelines Offer a collection of coding rules and guidelines. Make HDL Codes readable, modifiable, and reusable. Achieve optimal results in synthesis and simulation.