搜索资源列表
LabView-software-timing
- LabView中软件定时程序设计，包括介绍C++包如何使用。-LabView software timing in programming
Interpreting-the-Timing-Diagram
- 对The 68000 Read Cycle时序的分析-Interpreting the Timing Diagram to the 68000,A 68000 memory access takes a minimum of eight clock states numbered from clock state S0 to clock state S7
VESA-VIDEO-TIMING-DATA-STANDARD
- VESA VIDEO TIMING BLOCK EXTENSION DATA STANDARD
VerilogHDL-for-timing-design
- 这是一本关于如何进行硬件时序设计的文档，对时序设计困难的朋友很有帮助 VerilogHDL时序篇.pdf-This ebook is about the timing design in FPGA, very helpful
Timing-shutdown-procedures
- 定时关机程序源码 一个易语言的关机程序源码-The timing shutdown procedures source shutdown process is an easy language source
ADC-Timing-sampling-showed
- SmartArm3250实验平台（LPC3250）在winCE6.0中，ADC定时采样实验例程-SmartArm3250 experimental platform (LPC3250) winCE6.0 in the ADC timing sampling experiments routines
Timing-Analysis
- 关于VHDL/VERILOG进行EDA设计时序分析时需要注意的一些需要注意的问题及处理策略，保证相当实用，请需要的人参考-VHDL/VERILOG the EDA design timing analysis need to pay attention to some issues that need attention and treatment strategies, guaranteed to be quite practical
symbol-timing-synchronization
- QPSK平方律定时同步算法实现定时误差和定时恢复-QPSK square timing synchronization algorithm ，estimate timing error and timing error correction
6666-within-the-timing-program
- 6666以内的计时程序，可以做毕业设计，用c语言和proteus做的-6666 within the timing program, you can do graduate design with c language and Proteus
Xilinx-Timing
- Xilinx FPGA 时序约束资料，原厂出品，经典不需要理由-Xilinx FPGA timing constraint information, original, classic no reason
Intersection-signal-timing
- 交叉口信号配时设计程序，C++程序，计算时间-Intersection signal timing the design process C++ program, the computation time
clock-timing
- 单片机控制时钟的计时，定时等功能，实现秒表，倒计时等功能。-MCU clock timing, timing and other functions, stopwatch, countdown functions.
Timing
- 国外关于时序设计的一本非常好的书，写得非常详细，包括时序的分析的原理-Abroad on timing design of a very good book, written in great detail, including the principle of timing analysis, etc.
static-timing-analyze
- 特权同学主讲的FPGA设计的时序约束专题（STA部分）-Speaker privileged classmates timing constraints for FPGA design topics (STA section)
Timing-shutdown-of-small-procedures
- Vc++ 最近开发的源代码定时关机小程序,只是出于兴趣，和大家分享一下。-Vc++ recently developed source code timing shutdown of small procedures, just out of interest, and we share.
Xilinx-design-timing-constraints
- 很有用的Xilinx时序约束设计资料，很适合初学者-Very useful Xilinx timing constraints, design data, is very suitable for beginners
how-to-read-the-timing-diagram
- 一份让你知道如何看懂众多芯片时序图的好资料-Let you know how to read a timing diagram of good information
Timing-control-display-of-lights
- 指示灯定时控制显示。这是在CCS环境下运行的，是DSP的一个实验-LED timing control display. It is run under the CCS is an experimental DSP
timing-shutdown
- 该程序可以实现系统定时关机功能，简单方便。-timing shutdown
Robust-Freq-Timing-Syn-for-OFDM
- Robust Frequency and Timing Synchronization for OFDM.pdf OFDM系统一种经典的定时和频偏估计算法。 A very classical timing and frequency estimate algorithm。