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DS1302
- 本代码是控制DS1302的VHDL代码，浅显易懂，方便修改，注意看data sheet，保证时钟和各个延迟满足要求即可-This code is to control the DS1302' s VHDL code, easy to understand, easy changes, note the data sheet, ensure the clock and can meet the requirements of the
Verilog
- verilg 教程，学习verilog 非常好的一本书。-A usefull book for veriog learners.
Verilg-135samples
- verilogHDL程序设计 FPGA Design - Best Practices- FPGA Design- Best Practices
number_clock
- 典型实例 用FPGA来开发一个 数字跑表，实现跑表的全部功能-FPGA Verilg clock
random-maze
- 采用verilg语言并结合VGA显示、PS2接口技术、键盘输入等实现基于FPGA开发板的可选择性迷宫游戏。可以利用电脑键盘和显示器来玩这个游戏-Verilg language and to combine VGA display and the PS2 interface technology, the keyboard input to achieve optional FPGA development board based maz
traffic_light_ok
- 一个用verilg语言编写的信号交通灯的程序，可以在DE2的最小系统板里实现，经过验证的-A written language with verilg signal traffic lights program, can be in the minimum system DE2 board realization, validated
dacontrol
- 数字量转成模拟量的基于verilg hdl 语言编写的程序 非常好用-digital convert to analog
kebianjishuqi
- Verilg HDL语言编写实现进制计数器切换，包括模9、模6、模4、和模8加法计数器，通过按键输入，消抖，数码管显示。开发环境：ISE14.7-Verilg HDL language to achieve binary counter switch, including die 9, die 6, die 4, and die 8 adder counter, through the key input, eliminate jitt
fpga
- verilg语言实现测频 及与stm32以fsmc通信方式进行通信(Verilg to achieve frequency measurement and communication with STM32 in FSMC communication mode)
fredeng
- 用verilg语言实现等精度测量频率，最大可测100m。(Implementation of equal precision frequency measurement with verilg language)
tb
- 用verilog语言实现FPGA控制测频(The FPGA control measurement was realized with verilog language)