搜索资源列表
Verilog
- 用verilog实现七位最大公约数的算法，使用状态机，可仿真电路图-Seven with the greatest common divisor algorithm verilog implementation, the use of state machine circuit simulation
Verilog-HDL
- 这是关于VERILOG HDL的有限状态机的源码，大家参考参考，应该有好处的。-This is about VERILOG HDL source code for finite state machines, we refer to the reference, it should be good.
Verilog--coding--style
- Verilog可综合代码编写风格介绍。属于HW中央逻辑开发部的绝密资料，加上本人的总结而成。喷血推荐。-The coding style of Verilog language. It is very useful for verilog system developer
CRC-Generator-for-Verilog-or-VHDL
- CRC Generator for Verilog or VHDL-CRC Generator for Verilog or VHDL
sdr-sdram-(verilog)
- Altera的SDR SDRAM模型，verilog实现，带说明书文件以及仿真文件、SDRAM原型文件。-Altera' s SDR SDRAM model, verilog implementation, with manual files and simulation files, SDRAM prototype file.
Verilog-Digital-System
- Verilog数字系统设计教程-夏宇闻，详细介绍verilog语法及大量范例说明-Verilog Digital System Design Tutorial- Xia Yu Wen
slave-ram-verilog
- ram代码 用verilog写的，有文字说明-verilog code of ram
Verilog
- FPGA经典例子，可以让大家更好的学习Verilog HDL-Classic example of FPGA, allowing you to better learn Verilog HDL
verilog-usb--protel-design
- 基于FPGA的usb2.0 ip核设计，所用的语言是verilog-FPGA-based usb2.0 ip core design, the language used is the verilog
verilog-traffic-light
- 基于VerilogHDL设计的交通灯控制系统本设计利用Verilog HDL 语言、采用层次化混合输入方式,可控制4个路口的红、黄、绿、左转四盏信号灯,让其按特定的规律进行变化。 -This design using Verilog HDL language, adopt hierarchical mixed input method, four intersection control of red, yellow, green, l
Verilog-Round-Robin-Arbiter-Model.tar
- Verilog Round Robin Arbiter Model
1024FFT-verilog-hdl
- 基于spartan 3e 的IFFT算法verilog HDL程序-Based on the verilog 3e Spartan IFFT algorithm of HDL program
verilog
- verilog 一些语音模块 方便平时应用-verilog Module some useful speech module
Verilog-HDL_PPT
- 《数字系统设计与Verilog HDL（第4版）》课件-" Digital System Design and Verilog HDL (4th Edition)" Courseware
verilog
- 数字锁相环电路verilog源代码 开发环境quartus-Digital PLL circuit verilog source code
verilog-encoder
- JPEG的編碼器 使用VERILOG以硬體實現 也使用MODEL模擬驗證-JPEG encoder using the VERILOG hardware implementation is also used to simulate authentication MODEL
modelsim-for-verilog
- verilog或VHDL编辑仿真软件的使用方法，个人用过觉得很不错，所以在此推荐给大家-editing verilog or VHDL simulation software to use, personally feel very good used, so this recommendation to you
The-Verilog-Hardware-Description-Language-5E-(Tho
- The Verilog Hardware Descr iption Language 5E (Thomas & Moorby)
SDRAM-verilog
- SDRAM读写控制的实现与Modelsim仿真-verilog-SDRAM read and write control to achieve with the Modelsim simulation-verilog
verilog-ieee.pdf.tar
- IEEE 2001 verilog 标准 ,详细讲述了 业内 公认的 VERILOG 标准 ,-The Verilog¤ Hardware Descr iption Language (Verilog HDL) became an IEEE standard in 1995 as IEEE Std 1364-1995. It was designed to be simple, intuitive, and effective at