搜索资源列表
uart_verilog
- uart串行口,用Verilog编写的.供大家参考-uart serial port, using Verilog prepared. For your reference
ReadHexFile
- 将16进制文件转换成RAM可读的文件,verilog语言编写-229 to 16 documents into RAM readable document, verilog language
Verilogdianzirili
- 基于Verilog 的电子日历与电子时钟程序，可以进行调日期、星期、时间的分钟与小时，通过几种模式来显示日历与时间。-Verilog-based electronic calendar and e-clock procedures, can be adjusted date, week, time of minutes and hours, through several models to display a calendar and
4VerilogFIFO
- 一种新的FIFO实现方法,verilog描述，通过modelsim 6.0 仿真，Quartue综合-FIFO realize a new method, verilog descr iption, modelsim 6.0 through simulation, Quartue integrated
89_full_adder
- full adder设计代码，verilog 语言描述，通过modelsim 仿真，quartus综合-full adder design code, verilog language to describe, through the ModelSim simulation, quartus integrated
taix_fee
- verilog HDL编写的出租车计费系统-verilog HDL prepared Taxi Accounting System
FIFO
- 异步FIFO控制器的Verilog设计与实现-Asynchronous FIFO controller Verilog Design and Implementation
8251Verilog
- 通用串行异步收发器8251的Verilog HDL源代码,经过仿真验证。 -Universal Serial Asynchronous Receiver Transmitter 8251 the Verilog HDL source code, through simulation.
des
- 用VERILOG语言实现的数据加密标准代码,在QUARTUS5.1上仿真过-Using Verilog language code of the Data Encryption Standard, in the simulation had QUARTUS5.1
FIFO-DC
- FIFO的Verilog程序 已在modelsim中编译通过 并且可以通过DC进行综合-FIFO procedures have been in the Verilog in ModelSim compiler and can be passed through the integrated DC
2410ucos
- 基于Verilog HDL的电梯系统设计-Verilog HDL-based design of the elevator system
qiangdaqi(auto)
- 用verilog hdl硬件描述语言实现多人抢答器功能，有计时，计分，报警等功能。-Using hardware descr iption language verilog hdl people realize Answer feature, have timing, scoring and alarm functions.
I2C_controller
- verilog编写的一个简单的I2C控制器,言简意赅,完成对寄存器的配置.用户可自行修改配置参数.
bbb
- AVS运动补偿电路的VLSI设计与实现 提出了一种基于AVS标准的高效的运动补偿电路硬件结构，该设计采用了8 X 8块级流 水线操作，运动矢量归一化处理和插值滤波器组保证了流水线的高效运行以及硬件资源的最优 利用。采用Verilog语言完成了VLSI设计，并通过EDA软件给出仿真和综合结果。-AVS motion compensation circuit of VLSI Design and Implementation o
src
- 一个SDH中最基本传输模块STM-1的帧头检测器，verilog编程实现-A basic SDH transmission module STM-1 Header detector, verilog Programming
epp_sram
- verilog语言编写的FPGA代码。功能为pc机通过epp不断写数到sram中，然后pc发送中断信号打断写过程读取sram中的数据。rar包中包含epp协议，模块文件和测试文件（test）。-Verilog FPGA code languages. Pc machine functions through a number of epp constantly write to the SRAM, and then pc send in
rgb2yuv
- verilog编写，rtl风格，流水线设计，实现图像rgb格式到yuv格式的转换。-Verilog prepared, rtl style, pipeline design, realize image rgb to yuv format format conversion.
sc
- 用verilog编写的乒乓球游戏，内带ps2，VGA驱动，下载到spantan3开发板上即可使用（原创）-Prepared using Verilog table tennis game, with band ps2, VGA driver, download to spantan3 development board to use (original)
FIFO_synthesised
- verilog语言编写可综合FIFO。简单实用-Verilog languages can be integrated FIFO. Simple and practical
ad_7266_32_v1_00_a
- AD7266的Verilog驱动程序,已仿真通过,可直接在EDK下使用.