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bit_intealeaver1
- verilog HDL语言实现dvb_t中的比特交织器源代码描述-verilog HDL language dvb_t the bit interleaver source code Descr iption
i2cjiekouchengxu
- 这是一个IIC的接口程序，是夏宇闻编的书《verilog 数字系统设计教程》的IIC的源码，很通俗易懂-IIC interface procedures, Xia Wen is the book series "verilog Digital System Design Guide," the IIC the source, very user-friendly
NAND256R3A_VE1
- 256Mbits (x8) 528 Bytes Page, NAND Flash Memory Verilog HDL Model User Manual -256Mbits (x8) 528 Bytes Page, NAND Flash Memory Verilog HDL Model User Manual
E016_X-HDL3.2.52
- VHDL和Verilog代码互转工具,对EDA工程人员会有很大的帮助.-VHDL and Verilog code referrals tools, EDA staff to be very helpful.
verilogzzhwfy
- 用Verilog实现QPSK中的差分,扰码,串并,解差分,解扰码,解串并,用MUXPLUS2进行仿真-QPSK with Verilog realize the difference, code, and serial, Xie difference, encryption codes, and solutions Series, The simulation used MUXPLUS2
sdr_data_path
- SDRAM控制器Verilog员代码，数据链路模块，完成和顶层模块的数据交换-SDRAM controller member Verilog code, data link module, Top module completed and the data exchange
control_interface
- SDRAM控制器Verilog员代码，控制接口模块，完成和顶层模块的控制命令的传递-SDRAM controller member Verilog code control interface module, Top module and complete the transfer of control orders
Commandinterface
- SDRAM控制器Verilog员代码，命令生成模块，完成SDRAM控制接口命令的生成-SDRAM controller member Verilog code, order generation module, SDRAM interface complete control orders Generation
Anti_binarization
- H.264的 CAVLC的反二进制化的verilog code-H.264 CAVLC anti-binary code of verilog
chap6
- 《Verilog HDL 程序设计教程》3-"Verilog HDL Design Guide" 3
chap9
- 《Verilog HDL 程序设计教程》6-"Verilog HDL Design Guide" 6
chap11
- 《Verilog HDL 程序设计教程》8-"Verilog HDL Design Guide" 8
vhdltoverilog
- vhdl to verilog语言的编程设计，很有参考价值。-vhdl to verilog programming language design, great reference value.
VHDLverilogshirenqiangdaqi
- 用VHDL和verilog实现的四人抢答器-using VHDL and verilog realization of four Responder
uart_core_vhdlORverilog
- 串uart的vhdl，verilog，lattic实现原码 里面有四个文件,分别UART 源码 (lattice version)\uart 源码 (Verilog)\uart 源码 (VHDL)\uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respe
shuzimiaobiao
- 用verilog实现了一个数字秒表的设计-verilog achieved using a digital stopwatch Design
FIFO
- 一个可以综合的Verilog 写的FIFO存储器 内附文档说明-a comprehensive Verilog can write FIFO memory attached document shows
oc8051
- 8051的verilog实现，内附testbench,c语言调试程序-8051 verilog achieve, enclosing testbench, c language debugging procedures
FIFO_v
- FIFO的verilog实现，内附testbench和文档说明-FIFO verilog achieve, enclosing testbench and documentation shows
hdlc
- 该工程是基于verilog hdl 语言编写的帧传输协议HDLC帧的发送端代码，会用QUATUSII的人都应该知道如何使用，希望能给你带来帮助-The project is based on the language verilog hdl fr a me transmission protocol HDLC fr a me of this generation- Codes will be used QUATUSII people s