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148个verilog hdl小程序（有很多testbench）——
- 148个verilog hdl小程序（有很多testbench）——.-148 Verilog HDL small programs (many testbench) from Part
RS encoder(Verilog)
- RS编码的源代码使用Verilog在Xinloinx平台-RS coding using the source code in Verilog Xinloinx platform
Verilog-Semantics
- Synthesizable Verilo---syntax and semantics一本很好的关于verilog可综合设计的参考书-Synthesizable Verilo--- syntax and semantics a good Verilog synthesis of the reference design
verilog reference guide
- 一本全面的verilog参考书-a comprehensive reference book Verilog
verilog-clock
- 用verilog编写的多功能数字钟--Multifunctional digital clock written in verilog.
Verilog源码14
- Verilog源码14.rar-Verilog source 14.rar
verilog基础知识
- verilog基础知识.rar--Basic knowledege of verilog.
Verilog硬件描述语言教程
- Verilog硬件描述语言教程.rar--Verilog hardware descr iption language tutorial.
曼彻斯特编解码Verilog代码
- 曼彻斯特编解码Verilog代码 .zip-Manchester codec Verilog code. Zip
北航夏宇闻verilog讲稿ppt
- 北航夏宇闻verilog讲稿ppt-Northern Xia Wen Verilog scr ipt ppt
Verilog HDL Examples
- verilog的入门级别的例子（转载）-Verilog entry-level examples (reproduced)
Verilog 设计技巧
- 本文介绍了使用verilog语言进行硬件设计的一些基本技巧-This paper describes the use of Verilog hardware design language, the basic skills
Computer Architecture Handbook on Verilog HDL
- Computer Architecture Handbook on Verilog HDL
发一个基于ModelSim仿真的Verilog源代码包
- 发一个基于ModelSim仿真的Verilog源代码包-made a ModelSim simulation based on the Verilog source code
Verilog 语法速查手册
- Verilog 语法速查手册，做成了一个页面形式，方便Verilog开发人员查询！-Verilog Grammar Check manual, it would be a one page form to facilitate the development of Verilog staff inquiries!
verilog实现ALU的源代码
- verilog实现ALU的源代码，并提供了一个详细的测试平台！-achieve ALU Verilog source code, and provide a detailed test platform!
Verilog&Vhdl混语言对SDRAM的控制源代码
- Verilog&Vhdl混语言对SDRAM的控制源代码，提供了很好的例子，顶层文件为sdrm.v！-VerilogVhdl mixed language SDRAM control of the source code, provided a good example of top-level documents sdrm.v!
结合XILINXCPLD RS232通信(verilog)
- 结合XILINXCPLD所做的模拟RS232通信verilog源程序-XILINXCPLD combine the simulation RS232 communication Verilog source
能综合的YCrCb2RGB模块（verilog)_采用3级流水线
- 能综合的YCrCb2RGB模块（verilog)_采用3级流水线,用fpga做小数运算，还有就是流水线技术 -can YCrCb2RGB integrated module (Verilog) _ used three lines, they simply do with fractional arithmetic, there is pipelining technology
verilog SDRAM core
- 我用过的verilog hdl写的SDRAM core源程序,经过测试应用-I used to write Verilog HDL source of SDRAM core, the test application