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1_061026140305
- 基于FPGA的I2C总线模拟，采用verilog HDL语言编写。- Based on the FPGA I2C main line simulation, uses verilog the HDL language compilation.-FPGA-based I2C bus simulation, using verilog HDL language.- Based on the FPGA I2C main line simula
DDS+51
- 本程序功能: DDS文件夹内的程序，完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频. 可通过键盘操作设置频率参数和选择波形种类和控制运行. 由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "Verilog"文件夹内,是用Verilog语言编写的 FPGA 程序.-this program functions : DDS folder procedures, complete
memoryuse
- Verilog HDL语言在FPGA实现中的存储器的使用详细说明-Verilog HDL language in the FPGA memory of the use of detailed
epp_sram
- verilog语言编写的FPGA代码。功能为pc机通过epp不断写数到sram中，然后pc发送中断信号打断写过程读取sram中的数据。rar包中包含epp协议，模块文件和测试文件（test）。-Verilog FPGA code languages. Pc machine functions through a number of epp constantly write to the SRAM, and then pc send in
key
- 一个4*4矩阵键盘的VERILOG接口程序设计（FPGA）-A 4* 4 matrix keyboard interface program Verilog Design (FPGA)
i2c_slave
- 一个好用的经过FPGA验证的i2c_slave verilog代码。-After a useful FPGA proven i2c_slave verilog code.
ddr_ctrl
- verilog hdl coding DDR sdram control for fpga -verilog hdl coding DDR sdram control for fpga
FPGA--DDS-PhaseMeasure
- Verilog实现的DDS正弦信号发生器和测频测相模块，DDS模块可产生两路频率和相位差均可预置调整的值正弦波，频率范围为20Hz-5MHz，相位范围为0°-359°，测量的数据通过引脚传输给单片机，单片机进行计算和显示。-Verilog realize the DDS sine wave signal generator and frequency measurement module test phase, DDS module c
sdram_verilog_lattice
- 已经成功的FPGA 控制的SDRAM控制器代码.只要修改你需要的宽度就可以了.-FPGA has been successfully controlled by SDRAM controller code. As long as you need to modify the width of it.
verilog
- 卡内基梅陇大学verilog课程讲义.pdf,是verilog 学习者非常实用的优秀资源-Carnegie University Meilong Verilog Course Training Manual. Pdf, is very useful Verilog learners excellent resources
djpeg.tar
- jpeg格式到bmp格式的硬件实现，verilog开发，fpga 实现。-jpeg format to bmp format hardware realize, verilog development, fpga realize.
xp2syscloclkpll
- 这个是讲pll的具体用法的,一般在fpga设计中都会用到 他,这个是lattice的xp2的pll的介绍,不过,fpga 都是相通的其他两家也差不多-Pll say this is the specific usage, the general design in the FPGA will use him, this is the lattice of the pll of xp2 introduction, however, fpg
FPGA-jiangyi
- FPGA的很好讲义,对于初学者学习FPGA的相关知识具有较好效果.-FPGA good lectures, for beginners to learn the relevant knowledge FPGA with good results.
hdb3
- hdb3的发送端源代码，采用verilog可综合格式书写。已经在多款fpga和cpld芯片成功综合实现。-HDB3 sending client source code, Verilog can be used to write an integrated format. Has been in several FPGA and CPLD chip integrated to achieve success.
wp_max_flash
- FPGA中FLASH配置控制源码,VHDL和Verilog-FPGA source code in the FLASH configuration control, VHDL and Verilog
fpga
- fpga功能实现有限字长响应FIR 用verilog编写-FPGA functionality in response to the realization of finite word-length FIR prepared using Verilog
pci_express_crc
- PCI express CRC rtl core for Fpga/asic Designer
RS232
- FPGA实现RS-232串口收发的Verilog程序，已经调通。-FPGA realization of RS-232 serial port to send and receive the Verilog procedures, Qualcomm has been transferred.
DDS
- FPGA中实现基于查找表方式（LUT）的DDS实现，可用在数字下变频和COSTAS锁相环中，Verilog编写，本人已经调通-In FPGA-based lookup table approach (LUT) to achieve the DDS can be used in the digital down-conversion and COSTAS PLL, Verilog prepared, I have transferred
verilog
- 北大微电子学系于敦山老师的课件，介绍Verilog HDL、Cadence Verilog仿真器、可综合的Verilog HDL、设计举例、自动布局布线工具、Verilog的词汇约定等内容-Department of Microelectronics, Peking University in the teacher s courseware mts on Verilog HDL, Cadence Verilog simulator c