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VerilogHDL
- 数字系统设计与VerilogHDL（第3版）教案-Digital System Design and VerilogHDL (version 3) lesson plans
VerilogHDL
- 经典VerilogHDL语言例子48例,很好的学习verilog程序-VerilogHDL language classic example of 48 cases, good learning verilog program
c3
- VerilogHDL编写的8位加法器实现-bgfhgfhjgjhgj
VerilogHDL
- 数字系统设计与VerilogHDL 数字系统设计与VerilogHDL-Digital system design and digital system design and VerilogHDL VerilogHDL
VerilogHDL
- 不错的Verilog启蒙书 VerilogHDL程序设计与实践-Verilog Primer VerilogHDL good program design and practice
fenpinqi-VerilogHDL
- 各种分频器的VerilogHDL语言编写，有通过计数器实现的奇分频，偶分频，任意分频-Various divider VerilogHDL language, there is achieved through the odd frequency counter, even frequency, any frequency
fifo-VerilogHDL
- 利用VerilogHDL语言编写的同步FIFO，异步FIFO的编写及其注释-VerilogHDL language using synchronous FIFO, asynchronous FIFO, write and comment
multplier-VerilogHDL
- 利用VerilogHDL语言编写的各种各样的乘法器，比如并列乘法器，省时乘法器等-VerilogHDL language using a variety of multipliers, such as parallel multipliers, multiplier and other time-saving
key-board-and-mouse-VerilogHDL
- 键盘鼠标的原代码,用FPGA实现,使用VerilogHDL编写-Keyboard and mouse of the original code, FPGA, using VerilogHDL writing
VerilogHDL-tutorial
- VerilogHDL硬件描述语言教程，较详细的介绍了verilog的基本用法-VerilogHDL hardware descr iption language tutorial, more detailed introduction to the basic usage of verilog
verilogHDL-design-flow
- verilogHDL编程语言经典读本,IC设计师常用读本，用于FPGA快速开发-verilogHDL classic programming language readers, IC designers often readers, for rapid development of FPGA
VerilogHDL-literacy-text
- VerilogHDL扫盲文 适合刚刚接触Verilog HDL的同学。生动易懂-VerilogHDL literacy text for students new to Verilog HDL. Lively and easy to understand
V3.0-VerilogHDL
- VerilogHDL那些事儿V3.0 详细生动的介绍了Verilog HDL。-V3.0 VerilogHDL those things more lively introduction to the Verilog HDL.
VerilogHDL-V3.0
- 这是一本讲述verilogHDL的书籍，通俗易学，名字是《VerilogHDL那些事儿》-This is a book about verilogHDL, popular easy to learn, the name is " VerilogHDL that thing"
VerilogHDL-fpga
- 精通VerilogHDL：IC设计核心技术实例详解-Proficient VerilogHDL: IC design example explanation of core technology
VerilogHDL
- 《设计与验证：VerilogHDL》的配套源代码，有丰富的例子，有利于初学者使用-Design and Verification: Verilog HDL "supporting source code, a wealth of examples, for beginners
VerilogHDL-Code-Formatter-V1.2
- 这是一款Verilog代码格式化工具. 用于代码格式美化。您可以根据自己的VerilogHDL格式需求，在右侧控制面板中进行控制，左侧即时显示出当前设置的格式。是一款好用的VerilogHDL代码格式工具。-Format landscaping. According to their own VerilogHDL format requirements, you can in the right side of the control
VerilogHDL-for-timing-design
- 这是一本关于如何进行硬件时序设计的文档，对时序设计困难的朋友很有帮助 VerilogHDL时序篇.pdf-This ebook is about the timing design in FPGA, very helpful
VerilogHDL
- VerilogHDL程序设计教程，pdf文件格式-VerilogHDL programming tutorial pdf file format
VerilogHDL-v5
- VerilogHDL那些事儿_建模篇v5-VerilogHDL those things _ Modeling articles v5