搜索资源列表
decoder
- 一个verilog源代码，用于译码器的编程。-A verilog source code, for programming decoder.
iic
- 一个verilog源代码，可用ISE等实现，功能为I2C接口标准建模。-A verilog source code, can be used, such as the realization of ISE, the functional model for the I2C interface standard.
pwm_hw
- sopc nios ii学习资料介绍niosii 开发自定义外设pwm的verilog源代码-Learning sopc nios ii information on the development of custom peripherals niosii the verilog source code pwm
15252uP(1)
- 这是8位微处理器的Verilog源代码，可以欠在Flex10k10里面-This is the 8-bit microprocessor Verilog source code, can they owed in Flex10k10
8b10b_encdec
- 8b10b转换编码、解码verilog源代码-8b10b transcoding, decoding verilog source code
XPS_EMC
- Xilinx EDK中SOC使用外部存储器接口（EMC）的方法，并用ISP1581举例说明了如何与时分复用总线（8051单片机总线）设备进行连接，有Verilog源代码。-Xilinx EDK in SOC using external memory interface (EMC) methods, and examples of how ISP1581 with the TDM bus (8051 bus) devices to co
VERILOG-USB2.0IP-core
- 完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-VERILOG language with a complete development of USB2.0 IP core source code, including files, simulation files
YUV2RGB
- 关于YUV转RGB的verilog源代码、说明文档和modelsin仿真，相信对大家一定有很大的帮助，我费了好长时间才找到的！-YUV to RGB on the verilog source code, documentation and modelsin simulation, we believe that there will be a great help, I spent a good long time to find i
FPGA-DDS
- 在FPGA内，以查表方式实现频率直接合成器（DDS）功能。verilog源代码-In the FPGA in order to achieve the look-up table means the direct synthesizer frequency (DDS) feature. verilog source code
FPGA-IIC
- 在FPGA内，实现IIC数据接口。verilog源代码-In the FPGA, the realization of IIC data interfaces. verilog source code
8BitRISC_CPU(VERILOG)
- 8位risc内核源代码，内有体统框图，较其他详细。适合初学者学习-8-bit risc kernel source code, there are decency diagram, compared with other details. Suitable for beginners to learn
pci-verilog
- USB及PCI总线设计的一些源代码（经测试）-USB and PCI bus design some of the source code
arm7
- ARM7core verilog 源代码-ARM7 core verilog source code
trafficlight
- 已应用在北京某校园内的交通灯控制程序，可以自动控制，手动控制，可以输入设定时间等等。verilog源代码-Has been used in a Beijing campus traffic light control procedures can be automatic, manual control, you can enter the set-up time, etc.. verilog source code
sram_saa1117verilog
- 图像采集、存储控制verilog源代码，fpga控制SAA1117,采集数据存储到sram，仿真编译测试都能通过-Image acquisition, storage, control verilog source code, fpga control SAA1117, collecting data to sram, simulation tests can be compiled by
verilog
- 采用用verilog语言编写的全数字锁相环的源代码。-Verilog language used by all-digital phase-locked loop' s source code.
systemcaes_latest.tar
- 高级加密标准aes加密算法用fpga实现的Verilog源代码。-Advanced encryption standard aes encryption algorithm using fpga implementation Verilog source code.
rs232
- 完整的RS232 Verilog源代码，支持波特率可调，支持调试命令，配合串口调试工具，可作为FPGA开发中的调试平台。-Full RS232 Verilog source code, support for baud rate is adjustable to support debugging command, with the serial debugging tools can be used as the debugging
syn-fifo-verilog
- 用verilog语言写的同步FIFO设计源代码。-The source codes for syn-fifo using verilog language.
aescore
- 基于FPGA的AES算法实现的VERILOG源代码，对于信息安全专业研究AES算法的硬件实现很有用-FPGA-based AES algorithm implementation VERILOG source code, for the information security professional research of the hardware implementation of AES algorithm is useful