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MultiCLKCPU
- 本设计实现了多周期CPU的设计，运行环境是quatrus2；该多周期CPU可以处理22条32位指令（具体指令见源码，绝不坑人）。压缩包内含有源代码，程序模块表和实验报告以及详细的设计图，是学习verilog的好材料啊。-The Design and Implementation of a multi-cycle CPU design, operating environment is quatrus2 the multi-cycle
CPU
- 一个多周期CPU的完整设计，quartus平台，Verilog实现，内含实验报告，和详细的各模块功能表-Complete a multi-cycle CPU design, quartus platform, Verilog implementation, includes lab reports, and a detailed menu of each module
CPU
- 多周期CPU设计，使用Verilog HDL语言编程，实现MIPS的指令系统。-CPU design with verilog hdl language.Instructions from MIPS.Something in detial is not perfect.
MulticlockCPU.tar
- verilog hdl实现多周期CPU，按照有限状态己设计，含源码、实验报告和详细vsd电路图-verilog hdl multi-cycle CPU, in accordance with the finite-state has been the design, including source code, test reports and detailed schematic vsd
gongpinji
- 工频频率表设计。此设计单片机用1M的内部时钟，测多周期的方法减小正负1误差，精度可达到0.0008左右-工频频率表设计
lpc-matlab
- 这个MATLAB的代码集是通过多个程序实现语音信号的各种分析,包括清音浊音,计算自相关函数,计算基因周期等-The MATLAB code set is more than one program by a variety of voice signal analysis, including voiceless voiced, calculated from the correlation function to calculate
MulCylCPU
- 多周期cpu在VHDL中的verilog实现-More cpu cycles in the verilog implementation in VHDL
multicyclecpu
- 用于Spartan3实验板上的多周期CPU实现 开发环境为Xilinx10 已调试通过-used for spartan3 lab board multi-cycle CPU implementation for xilinx 10
CPU
- 用硬件编辑语言，实现一个多周期cpu 的内核部分。-Editing language in hardware to achieve a multi-cpu core part of the cycle.
CPU-source-code
- CPU设计代码，包括单周期CPU，多周期CPU，流水线CPU及相关ALU组件。-CPU design code, including single-cycle CPU, multi-cycle CPU, ALU pipeline CPU and related components.
multi_cycle_cpu
- 多周期cpu,multi_cycle_cpu，南京大学计算机系计算机组成原理实验-Of multi-cycle cpu, multi_cycle_cpu, Nanjing University Department of Computer Science Computer principle experiment
CPU
- 多周期cpu结构有特点，性能优良，便于理解。-This cpu is very good.It is easy to understand.
singlePcyclePMIPS2
- 多周期MIPS实现的CPU设计方案，包括源码-MIPS multi-cycle
simpleCPU
- 一个简单的多周期CPU的实现，verilog语言实现，结构较简单，欢迎分享-A simple multiple CPU,based on language verilog
MDP-model-of-MPNP
- 在matlab平台上，针对多周期报童问题，采用值迭代算法、策略迭代算法和强化学习算法求解MDP模型的实例-This is an example presentting how to apply value-iteration algorithm，policy-iteration algorithm and reinforcement learning algorithm to MDP model, which aims to solve
PipelineCPU
- 用Verilog HDL语言或VHDL语言来编写，实现多周期CPU设计。能够完成以下二十二条指令。（均不考虑虚拟地址和Cache，并且默认为大端方式）： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, im
fftinMCR
- matlab fft多周期各采样点在电力电子上的谐波分析，采样频率2000，总采样点数1320，通过输入数据文档txt文件名，实现绘图及THD分析-matlab fft multi-cycle of each sampling point on the harmonic analysis in power electronics, the sampling frequency of 2000, the total number of s
cycle_code
- verilog实现了MIPS多周期（5周期）的CPU-verilog MIPS 5 cylce
DSP_mutipile_MIPS_CPUcode
- 32位多周期MIPS微处理器设计代码。具体功能： 运行下列的6类32条MIPS32指令。 算术运算指令：ADD、ADDU、SUB、SUBU、ADDI、ADDIU。 逻辑运算指令：AND、OR、NOR、XOR、ANDI、ORI、XORI、SLT、SLTU、SLTI、SLTIU。 移位指令：SLL、SLLV、SRL、SRLV、SRA。 条件分支指令：BEQ、BNE、BGEZ、BGTZ、BLEZ、BLTZ。 无条件跳转
mips-VHDL
- 自己作业代码，应用VHDL语言实现一个多周期的简单MIPS核-AlphaJob code, the application of VHDL language more than one cycle of a simple MIPS core