搜索资源列表
zhong
- LED数字钟,使用8位数码管显示,中断定时-LED digital clock, using 8-bit digital control, timer interrupt
clock
- 液晶数字钟汇编程序,忘多指点,相互学习,学习中-LCD digital clock assembler, forget multi-pointing and mutual learning
CLOCK_FINAL
- 8051单片机的数字钟汇编程序,可以实现闹铃-8051 digital clock assembler, can alarm
Counter60min
- VHDL语言编写的一个六十进制计数器(用于分钟),一个脉冲输入引脚,一个复位引脚,8个BCD码输出引脚,一个进位输出引脚。与我的其它8个模块配套构成一个数字钟。-A 60 binary counter(for minute) programmed with VHDL language.A pulse input, a reset input, eight BCD code output BCD code, a carry bit out
Counter60sec
- VHDL语言编写的一个六十进制计数器(用于秒),一个脉冲输入引脚,一个复位引脚,8个BCD码输出引脚,一个进位输出引脚。与我的其它8个模块配套构成一个数字钟。 -A 60 binary counter(for second) programmed with VHDL language.A pulse input, a reset input, eight BCD code output. It is one of my total
Debounce
- VHDL编写。在CPLK开发板上设计的数字钟的去抖动电路。该模块相对独立,是学习去抖动的好资料。该模块跟我其它的8个模块配套构成一个数字钟。-Programmed with VHDL.A debouncing circuit which is part of a digital clock designed on a CPLD development board.The module is independent from others
Displayer
- VHDL编写的针对八段数码管的显示译码电路。实现动态扫描输出小时、分钟和秒。是基于CPLD开发板设计的一个数字钟的一部分。-Programmed with VHDL.The decoding and displaying circuit for 8-segments displayer.It outputs the data of hour,minute and second in order with dynamic scaning
Distributer
- VHDL编写的分频器。用于将50MHz的时钟脉冲分频成一个500Hz的扫描时钟和1Hz的秒脉冲。与我的其它8个模块配套构成一个数字钟。-Programmed with VHDL.A clock distributer which generates a 500Hz scaning clock and a 1Hz second impulse. It is one of my total 9 modules that are used
FlashTime
- 用VHDL编写。称为校时闪烁电路。一般的电子表在校时时都会使被校正的时间不停地闪烁。此模块实现了类似的功能。与我的其它8个模块配套构成一个数字钟。 -Programmed with VHDL. It is called a flashing circuit(when time is being revised).Generally, a digital watch will flash the currently revised t
RvsTime
- 用VHDL编写。数字钟校时电路,根据表示是否校时的输入引脚、是校正小时还是校正分钟的输入引脚决定校正状态。接受一个按钮的脉冲输入,每输入一个脉冲,被校正的时间增加1.与我的其它8个模块配套构成一个数字钟。-Programmed with VHDL.The time-revising circuit of a digital clock. Detect the inputs and decide if revise time, hour
ADigCLK
- 用VHDL编写的一个数字钟。该模块是顶层模块,用VHDL例化语句例化各个子模块并组装成一个完整的数字钟。与我的其它8个模块配套构成一个数字钟。 -A digital clock programmed with VHDL.This module is the top-level module, it utilizes the Component instantiation of VHDL to incorporate all subm
KH-310
- KH-310 使用说明书以及部分设计,比如LCD驱动控制、数字钟设计、交通灯控制设计等。-KH-310 introduction
LEDshuzizhong
- 基于8086的数字钟设计,有具体过程,包括流程图,注释等-8086-based digital clock design, with specific processes, including flow charts, annotations, etc.
complete
- 用Verilog编写的数字钟与汽车尾灯模块。其中数字钟具有时间显示的基本功能,按键校时校分,闹钟模块(包含校时校分),仿电台报时(四低一高),整点报时,12-24显示切换等强大功能。-With a digital clock in Verilog modules and automotive taillights. Digital clock which displays the basic functions of a time, s
proteus-simulation-clock
- 以51单片机为控制器,实现数字钟,12864显示,proteus 仿真 模拟时钟-To 51 for the controller chip, digital clock, 12864 show, proteus simulation clock
timer
- 基于单片机的数字钟,基于汇编语言。基于单片机的数字钟,基于汇编语言。-Microcontroller based digital clock, based on assembly language
clock
- 数字钟的实现,其中包括闰年的实现,万年历的实现。-It is very good, but it has something wrong.
FINAL
- 汇编语言写的数字钟程序,带闹铃功能和设定功能-Digital clock written in assembly language program with alarm function
shizhong
- 计时数字钟,可以24小时循环计时,用单片机来实现,汇编语言简单易懂-Time digital clock, 24-hour cycle time, using single chip to achieve, assembly language easy to understand
clock2
- 数字钟源程序代码,c编程,带校时闹钟功能,适合51单片机使用-Digital clock source code, c programming, with the school when the alarm clock for 51 single use