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lmgui2
- 这个是evc下编写的状态机程序，大家可以学习下-prepared with the state machine procedures, we can learn under
moore state_machine
- 这是一个moore状态机的典型程序，供初学者参考-This is a typical state machine moore procedure reference for beginners
Verilog-statemachine
- 利用Verilog编程实现状态机的例子。很不错的。-use Verilog Programming state machine example. Very good.
MazeWalkerMaze
- 用有限状态机实现的迷宫求解。本程序用于画图的是OpenGL.-finite state machine to achieve the maze solving. The procedure for drawing the OpenGL.
statemachine_mult
- veilog实现的状态机乘法器.可以参考-veilog achieve the state machine multiplier. Can reference
statemachine11.2
- 推荐下载,verilog状态机实例.体现了流水线思想的应用 -recommend downloading Verilog state machine example. Pipeline reflects the thinking of the application
8.10
- 强烈推荐下载,verilog状态机实例.可以在modelsim下运行. -strongly recommend downloading Verilog state machine example. In modelsim running.
svpwm_zp
- 一个简单明了的电压空间矢量pwm程序，可以帮助你理解dsp自身的空间矢量状态机。-a straightforward space vector PWM voltage procedures can help you understand dsp their own space vector state machine.
uart_VHDL
- uart的vhdl实现代码 分模块设计和状态机设计 不错的，用它没错-UART achieve the VHDL code modular design and state machine design good, the right to use it
statemachine
- 自己做的一个关于more状态机的三种描述的比较。以后会有更多的资料，请大家关注。-doing more of a state machine on the three described earlier. Many more information, please everyone's attention.
menu_osd
- 关于嵌入式PCB板UI的程序，包含状态机等一些程序。-on Embedded PCB UI procedures, such as state machine contains some of the procedures.
FSM_program
- 用于协议状态机的编程参考，可以用于协议设计。-agreement for the state machine programming reference design can be used in the agreement.
112345
- 一篇经典状态机设计的资料，希望对大家有用-a classic state machine design information and useful for all
xcv
- verilog编写的状态机检测00100序列. 实现 input:...011000010010000... output:...000000000100100... 并且 用测试模块来验证状态是否正确工作-verilog prepared by the state machine detected 00,100 sequences. Achieve input : ... ... 011000010010000 outp
alarm_ok_1
- 用ATmega16实现的多功能带音乐闹铃（老鼠爱大米）的数字时钟，有3个功能键设置。具体功能为：秒表计时，闹铃音乐，时钟，校时设置。可以学习状态机的编程思想。-ATmega16 achieve with the music with multi-function alarm (Lao Shu Ai Da Mi) digital clock, There are three function keys installed. Specifi
trafficLight-verilog
- 交通灯状态机的实现，用verilog HDL编程，Xilinx ISE 6仿真，在实际电路中得到验证．-traffic lights to achieve the state machine, with verilog HDL programming, Xilinx ISE 6 simulation, the actual circuit have been tested.
other1234fdsfsfsfsffssfwerfdwefsfewfsfsfsf
- labview 状态机 希望站长可以开此分类~ 虚拟仪器开发与设计-PC FSM hope the station can be set this classification ~ Virtual Instrument Design and Development
16bit_booth_multiplier_STG
- verilog程序，实现两个16bit数乘法，采用booth算法，基于状态机实现，分层次为datapath和controller两个子模块，testBench测试通过-verilog procedures, two 16bit multiplication, the algorithm used booth. Based on the state machine achieved at different levels for data
0809conventorvhdl
- 1.AD0809转换器的vhdl实现 2.用状态机来实现不同状态的动态切换，思路明晰简单实现。 3.内含注释，易于修改和理解 4.对数码管的动态扫描,显示 -1.AD0809 converters to achieve the two vhdl. Using the state machine to achieve the different states of dynamic switching thinking, c