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time123456
- 智能计数器，对外部信号脉冲进行计数，并将脉冲个数显示出来。 基本要求：计数至少65536个脉冲，并将脉冲个数显示出来。 -intelligent counter, the external signal pulse counting, pulse number will be displayed. Basic requirements : at least 65,536 Count pulse, and pulse number
countqi
- 计数器 同步异步预置数清零 verilog hdl 编写-Asynchrony preset counter reset the Verilog HDL few prepared
2460100Time
- 24,60,100进制的计数器，还有数字时钟，欢迎下载哦~-24,60,100 229 of the counter, digital clock also welcome to download oh ~
sf10042
- c计数器的简单实现,使用VC++开发环境,没有密码,解压后直接可用-c counter the simple realization, the use of VC development environment, no password, unpacked directly available
counter60
- 这是我们做的一个作业 摸60计数器，用Quartus ii 做的 ，内容齐全 不可不看。-This is the one we do feel 60 counter operation with Quartus ii do. complete contents can not see.
MCU-counter
- 用verilog实现单片机计数器 用verilog实现单片机计数器-MCU with verilog counter with MCU counter verilog
counter1
- vhdl 计数器源程序，大家看看吧 vhdl 计数器源程序，大家看看吧-vhdl counter source, we see it vhdl counter source, we see it
mod6_cnt
- 一个用VerilogHDL语言编写的模6的二进制计数器-a Verilog HDL language used in the preparation of the six-binary counter
MSC51
- 单片机MSC51设计的5个源程序：1、数据排序2、多功能数字钟设计3、P1口循环亮灯设计4、脉冲计数器5、8250芯片串口扩展。另附程序详细介绍。 -microcontroller design MSC51 five sources : 1, 2 ranking data, multi-function digital clock design 3, I P1 lighting design cycle 4, pulse count
11223344scan_led1000
- Quartus环境下的1000进制计数器的扫描显示电路-Quartus environment under the 1000 counter-band scanning display circuit
9coolSQL
- 使用Asp+Access+FSO+Jmail+Servu开发，安装简单，操作简便、无需专业的知识及繁琐的设置，整站完全通过后台WEB界面管理，可运行于所有Windows平台（含虚拟主机)，采用完善的绝对物理路径模式，强大的上传及在线编辑功能，自动检测用户上传的文件，管理员可自定义设置过滤非法字符或代码(如asp*语句、*网站信息)，支持Serv-U5.0以上所有版本，结合Serv-U，具有实时注册及开通FTP功能，并区别于一般的虚拟
keyuzhide8bitconter
- 可预置的8位计数器程序的主要部分分析，用C语言开发！-can preset counter the eight major part of the process, with C-language development!
VHDL_clock
- 用VHDL能进行正常的时、分、秒计时功能、分别有6个数码管显示24小时、60分钟、60秒钟的计数器显示。-VHDL can be used for normal hours, minutes and seconds timing were six LED display 24 hours 60 minutes, 60 seconds showed that the counter.
COUNT_10
- VHDL源代码.设计一个带有异步清0功能的十进制计数器。计数器时钟clk上升沿有效，清零端为clrn,进位输出为co。 -VHDL source code. Asynchronous design with a 0-counter function of the metric system. Counter clock clk ascending effective end to reset clrn, rounding outpu
VerilogHDLshejifengpingqihe32weijishuqi
- 本文件介绍的是用VerilogHDL语言设计分频器和32位计数器.-This paper presents the design using Verilog HDL language Frequency Divider and 32 counters.
p1_port
- 单片机C51典型应用设计源码 包括液晶，串口，定时器计数器等内容-80C51 typical application design source including LCD, Serial, timer counter, etc.
conter1
- 一个VHDL计数器。可进一步改装成实际的计数器使用-a VHDL counter. Can be further converted into actual use of the Counter
Counter8
- ATmega8515 avr单片机做的计数器程序，自己试试看哦！适合初学者。-ATmega8515 microcontroller avr do counter procedures to try it for yourself! For beginners.
binarycount
- PROTEUS仿真PIC16F877的例子，是一个二进制的计数器-PROTEUS simulation PIC16F877 example is a binary counter
4_10_vhdl
- 这是老师给但计数器程序，经过自己刚才调试过了，真的成功了，哈哈……，有需要就看看吧-This the teacher but to counter procedures, testing himself just over a really successful, ha ha ... there is a need to watch it!