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pll
- 该程序实现的锁相环,运行环境为matlab,二阶的环路滤波器
PLL
- 国外一篇很好的数字锁相环(PLL)设计文档(解压后PLL.pdf),不可不看呦!
pll
- 用FPGA实现数字锁相环,开发环境为ISE
loop
- 对锁相环路的仿真,二阶环的仿真与分析都可以通过这个文件来到完成-Simulation of PLL, second-order loop simulation and analysis can be completed by the adoption of the document came
dangonghujiaofasheji
- 发射部分采用锁相环式频率合成器技术, MC145152和MC12022芯片组成锁相环,将载波频率精确锁定在35MHz,输出载波的稳定度达到4×10-5,准确度达到3×10-5,由变容二极管V149和集成压控振荡器芯片MC1648实现对载波的调频调制;末级功放选用三极管2SC1970,使其工作在丙类放大状态,提高了放大器的效率,输出功率达到设计要求。-Part of the launch phase-locked loop frequen
CyclonePLL
- Cyclone™ FPGA具有锁相环(PLL)和全局时钟网络,提供完整的时钟管理方案。Cyclone PLL具有时钟倍频和分频、相位偏移、可编程占空比和外部时钟输出,进行系统级的时钟管理和偏移控制。Altera® Quartus® II软件无需任何外部器件,就可以启用Cyclone PLL和相关功能。本文将介绍如何设计和使用Cyclone PLL功能。 PLL常用于同步内部器件时钟和外部时钟,使内部工作的时
Pll
- 锁相环解调调制信号,效果很好,这是电路pcb板-Phase-locked loop demodulation modulation signals with good results, this is the circuit board pcb
PllLogicModel
- 用Verilog语言编写锁相环(PLL)的经典文章,很实用!-Verilog language with phase-locked loop (PLL) classic article, very practical!
PLL(pdf)
- 锁相环的设计方法介绍(PLL),可作为设计的参考。-Design method for PLL (PLL), can be used as a reference design.
PLL
- 锁相环simulink源码,难得的好代码,不要错过!-PLL simulink sourcecode is a good program,please download now!
pll
- 由锁相环改变时钟,希望能帮助到大家,同时也希望大家多指教-Changed by the PLL clock, hoping to help to you, but I hope you teach more
pll(FPGA)
- 利用VHDL语言对FPGA进行锁相环倍频,经调试已经在开发板上实现倍频-The FPGA using VHDL language PLL frequency multiplier, the debug board has been achieved in the development of frequency
PLL
- 三项锁相环:利用park变换和clark变换,将三相电网电压,变换为两相旋转坐标系下的电压。同时跟踪A相电压的相位角-Three phase-locked loop: the use of park conversion and clark transformation, the three-phase voltage, transformed into two-phase rotating coordinate system volt
Matlab-based-simulation-PLL-design-
- 基于Matlab仿真的数字锁相环的设计进行了详细的分析和模拟,数字和模拟锁相环的论文-Matlab-based simulation of digital PLL design, a thesis on digital and analog phase-locked loop for a detailed analysis and simulation
PLL
- 30MHz-200MHz PLL锁相环,硬件电路,控制程序,原理图使用ORCAD,PCB使用POWERPCB5.0,控制程序使用KEIL C-30MHz-200MHz PLL phase-locked loop, the hardware circuit, control procedures, schematics using ORCAD, PCB use POWERPCB5.0 control program uses KEIL C
PLL
- 在FPGA里加入时钟锁相环,输出多种时钟,最后用modelsim对源代码进行了仿真处理;-Join clock PLL simulation
PLL
- PLL锁相环仿真文件,附带解释,完美实现(PLL phase locked loop simulation file, with explanation, perfect realization)
DDSRF-PLL
- 本文论述了在控制的一个重要方面电网连接的电源转换器,即检测基波正序分量的电网电压不平衡和扭曲的条件下。明确地,提出了一种积极的基于一种新的序列检测器双同步坐标系的解耦锁相环(双dq–PLL),完全消除了检测误差传统的同步参考框架(SRF–锁相环PLL)。(This paper deals with an important aspect in the control of grid connected power converters,
pll
- 一个简短的锁相环程序,主要是和频率与相位阶跃有关的,里面有详细注释(A short phase-locked loop program, which is mainly related to frequency and phase step, with detailed comments)
pll
- 封装的matlab程序,实现数字锁相环的功能函数(Encapsulated matlab program to implement the function function of the digital PLL)