搜索资源列表
DDR2_hardcore_userguide
- xillinx Spartan6 FPGA DDR 接口设计指南-xillinx Spartan6 FPGA DDR Interface Design Guidelines
DDR_SDRAM
- DDR——SDRAM学习资料,DDR——SDRAM学习资料-DDR- SDRAM learning materials, DDR- SDRAM learning materials
DDR_controller_verilog
- ddr的控制程序,用verilog实现的,非常的具体。-ddr
ddrsdram_verilog
- 内附doc是DDR SDRAM 参考设计文档;model包含SDRAM Verilog的模型;simulation包含verilog测试平台、modelsim工程文、设计库函数;source包含verilog源文件;synthesis包含工程的综合文件 。-Enclosing the doc is a DDR SDRAM reference design documentation model contains SDRAM Veril
DDRSDRAM_VHDL
- 内附doc是DDR SDRAM 参考设计文档;model包含SDRAM VHDL的模型;simulation包含VHDL测试平台、modelsim工程文、设计 库函数;source包含vhdl源文件;synthesis包含工程的综合文件。-Enclosing the doc is a DDR SDRAM reference design documentation model contains SDRAM VHDL model
tips_vhdl
- 包含图像采集、i2c设计及混合语言仿真、DDR控制器以及一些小程序,供学习使用-Includes image acquisition, i2c design and mixed-language simulation, DDR controller, and a number of small programs for learning to use
ddr_sdr_V1_1
- DDR控制器 - 用XILINX Virtex II FPGA实现 - 使用DDR MT46V16M16作为仿真模型 - 通用化-DR SDRAM Controller Core - has been designed for use in XILINX Virtex II FPGAs - works with DDR SDRAM Device MT46V16M16 without changes -
ddr_contrl
- DDR controller source code and test bench in VerilogHDL. It is very useful to develop DDR project.-DDR controller source code and test bench in VerilogHDL.
DDRcontrol
- DDR控制器的设计参考,包含有中文说明文档-DDR controller design for reference, including documentation in Chinese
DDR2SDRAM
- 使用MIG工具生成DDR控制器的技术介绍-Using the MIG tool to generate the DDR Controller Technology
xapp702
- 用Virtex4系列FPGA实现DDR控制器的技术介绍-With Virtex4 series FPGA to achieve DDR Controller Technology
S3C6410_wince6.0
- S3C6410 wince6.0 DDR 从128MB 扩展为256MB-S3C6410 wince6.0 DDR expanded from 128MB to 256MB
doc17414x90
- ddr设计控制器,源代码!Verilog代码!-设计控制器,源代码!Verilog代码!
ddr2_controller
- DDR2控制器设计原码,可以在FPGA上测试通过,并对外部的ddr memory进行读写访问.-DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access.
Twister_DDR_SDRAM_Board_Manual
- Twister DDR EP1C6Q240 FPGA 开发板 原理图,PCB,BOM-Twister Board Documentation Schematics, PCB and BOM Rev. B
mem-ctrl-rtl
- 实现对ddr的控制,可以在fpga的仿真环境下跑程序,并有testbench可以参考-implement ddr control
ddr_sdram_controller
- DDR SDRAM Controller design
DS-0050_OXE800SE_datasheet
- SATA NAS SOC,200MHz ARM926EJS核 SATA接口的NAS用处理器,集成USB2.0 HOST接口,Ethernet控制器,DDR SDRAM控制器,PCI HOST接口,可以扩展PCI外设。-SATA NAS SOC,NAS COntroller with 200MHz ARM926EJS core, intergated SATA controller,USB2.0 HOST controller,Ether
HY5DU121622CFP
- 64MB 512Mb, 16bit, DDR SDRAM MEMORY
ddr-sdram-verilog-resource
- 描述了ddr_sram的源代码,包括SDRAM的引脚功能介绍和Verilog在modulesim及quartus ii的实现-descr iption the resource code of ddr_sram