搜索资源列表
DDR_SDRAM
- ddr sdram 的控制程序，lattice的，比较好用的，大家-ddr sdram control program, lattice, and relatively easy to use, and we look
Altera_DDR_controller_core
- Altera DDR SDRAM控制器完整Verilog代码包，包括Verilog源代码，Doc说明文档，仿真DDR芯片模型，仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, descr iption documents, DDR verilog model and simulation testbench are all included.
DDRSDRAMconclude
- DDR SDRAM技术总结 介绍DDR SDRAM的一些概念和难点 着重讲解主流DDRII的技术 最后结合硬件设计提出一些参考 -DDR SDRAM DDR SDRAM Technical Summary describes some of the concepts and difficult to explain the mainstream DDRII technology focused on the final hardware
XAPP200_ddr_sdram_64b
- Xapp 200 64 bit DDR SDRAM design files for Xilinx Vertix
DDRSDRAM_controller
- ddr sdram控制器，lattice器件的参考设计，比较详细-ddr sdram controller, lattice components of the reference design, very detailed
ddr
- DDR solution for problem in NPC contest
ddr_100Mhz_2011.03.12
- 这个工程是用xilinx的MIG生成的对于spartan 3E的实验板的ddr的控制器，我已经能够在上面修改之后加入自己的思想，包括两个dcm的模块。-This project is the MIG generated by xilinx spartan 3E development board for the ddr controller, I have been able to modify the above by adding
DDR-failure-analysis
- DDR failure analysis
DDR-SDRAM
- 本应用指南描述了在 Virtex™ -4 XC4VLX25 FF668 -10C 器件中实现的 DDR SDRAM 控制器。该实现运用了直接时钟控制技术来实现数据采集，并采用自动校准电路来调整数据线上的延迟。-This application note describes a Virtex ™ -4 XC4VLX25 FF668-10C to implement the DDR SDRAM device contro
DDR
- 关于DDR布线规范，用于指导PCB布线.-Wiring on the DDR specification, PCB layout for
emb-dev-c3-appsel
- vhdl code for altera ddr design
TEST-BENCH.vhd
- test bench for ddr 1
tests
- 6437开发板测试程序,RAM,DDR,LED,RTC,USB,VIDEO,SPIROM-DM6437 DEMO program
model
- 用vhdl写的 ddr sdram 控制器,数据位可以修改。在quartus2下仿真通过-With written ddr sdram controller vhdl
DDR
- S3C6410 ARM11的DDR裸机驱动编程，使用RVDS2.2配置j-linkV8调试，启动方式是nandflash-S3C6410 ARM11 DDR bare-metal programming, using the RVDS2.2 configuration j-linkV8 commissioning, start-up mode is nandflash
ddr_model_c3
- DDR仿真模型，采用erilong语言，FPGA开发DDR控制器必备-DDR simulation module verilog
400-Mbs-DDR-Controller
- 这个应用描述了怎样在Xilinx环境下，通过MIG实现DDR控制器-Synthesizable 400 Mbs DDR SDRAM Controller
DDR-with-CoolRunner-II
- 详细讲解了CoolRunner II CPLD与DDR SDRAM的接口设计-Explained in detail about the design of the CoolRunner II CPLDs and DDR SDRAM interface
ddr
- 在SEED-DEC6437中DDR用于存储视频的缓冲数据！-Used to store video buffer data in the SEED-the DEC6437 the DDR!
DDR-SDRAM
- DDR SDRAM的设计，包括DDR SDRAM控制器，以及Modelsim仿真-The design of DDR SDRAM, DDR SDRAM controller, and Modelsim simulation