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异步fifo的两种经典设计
- 异步fifo的两种经典设计，英文文章，里面含有verilog源代码
异步FIFO存储器的控制设计
- 异步FIFO控制器的设计 主要用于异步先进先出控制器的设计。 所用语言Verilog HDL.-asynchronous FIFO controller design for the main asynchronous FIFO controller design. The language used Verilog HDL.
FIFO
- 异步FIFO控制器的Verilog设计与实现-Asynchronous FIFO controller Verilog Design and Implementation
FIFO
- 介绍异步FIFO结构的，对搞微电子的有用-Asynchronous FIFO structure introduced on the usefulness of engaging in micro-electronics
FIFO
- 异步FIFO verilog实现 异步FIFO verilog实现 -Asynchronous FIFO verilog realize realize asynchronous FIFO verilog
fifo-1117
- 这是异步FIFO的VHDL实现代码，已经在FPGA上通过实践证明，运行状态良好-This is the asynchronous FIFO realize the VHDL code, the FPGA has been proved through practice, running in good condition
fifo
- 使用VHDL编程的异步FIFO程序 经调试可运行-Using VHDL programming asynchronous FIFO procedure can be run by the debugger
fifo
- 用双端口ram实现异步fifo，采用格雷码，避免产生毛刺。-Using dual-port ram realize asynchronous fifo, the use of Gray code, avoiding the production of burr.
FIFO
- 异步FIFO的实现，可综合，可验证] keywords:almost_full,full,almost_empty,empty-The realization of asynchronous FIFO can be comprehensive, verifiable] keywords: almost_full, full, almost_empty, empty
FIFO
- 通用异步FIFO设计的verilog代码，来自于opencore-Universal Asynchronous FIFO Verilog design code, from opencore
fpga.fifo
- 异步FIFO是用来适配不同时钟域之间的相位差和频率飘移的重要模块。本文设计的异步FIFO采用了格雷（GRAY）变换技术和双端口RAM实现了不同时钟域之间的数据无损传输。该结构利用了GRAY变换的特点，使得整个系统可靠性高和抗干扰能力强，系统可以工作在读写时钟频率漂移达到正负300PPM的恶劣环境。并且由于采用了模块化结构，使得系统具有良好的可扩充性。-Asynchronous FIFO is an important module wh
FIFO
- 用verilog实现异步FIFO，代码中有两个模块，使用时注意顶层模块和底层模块，用quartus2即可打开直接使用。-Verilog using Asynchronous FIFO, the code has two modules, when the attention of top-level module and the bottom module, with direct access to open quartus2.
fifo
- 异步fifo的经典讲解，包括亚稳态的产生，同步电路的构造，fifo电路的结构，源代码实现。-Asynchronous fifo on the classic, including the emergence of metastable, the structure of synchronous circuits, fifo circuit structure, the source code to achieve.
Asynchronous-FIFO-design
- 异步FIFO是一种先进先出的电路，在异步电路中，由于时钟之间周期和相位完全独立，因而数据丢失概率不为零。如何设计一个高可靠性、高速异步的FIFO是一个难点，本代码介绍了一种解决方法。-Asynchronous FIFO is a kind of advanced first out circuit, in asynchronous circuit, as the clock cycle and phase between full in
fifo-VerilogHDL
- 利用VerilogHDL语言编写的同步FIFO，异步FIFO的编写及其注释-VerilogHDL language using synchronous FIFO, asynchronous FIFO, write and comment
FIFO Design
- 异步fifo设计经典文章，可作为异步fifo设计基础导读(Asynchronous FIFO design classic article, can be used as the basis for asynchronous FIFO Design Guide)
fifo
- 异步FIFO 输入: 16bit 输出:16bit 深度:256(Asynchronous FIFO Input: 16bit Output: 16bit Depth: 256)
异步FIFO设计
- 经典的异步FIFO设计，First Input First Output的缩写，先入先出队列，这是一种传统的按序执行方法，先进入的指令先完成并引退，跟着才执行第二条指令。(Classic asynchronous FIFO design)
异步FIFO
- 自己编写的同步和异步FIFO的verilog代码，验证过，有可靠性(Verilog code of my own synchronous and asynchronous FIFO, verified,and reliable.)
异步FIFO
- 纯Verilog实现的异步FIFO，分为读写控制模块，SRAM CORE，同步等几个模块，内含源文件和仿真文件(The asynchronous FIFO implemented by Verilog is divided into read-write control module, SRAM core module and synchronization module)