资源列表
[汇编语言] Binary_Division
说明:Assembly code for 32-bit binary division for 8051 series<mukund> 在 2025-06-21 上传 | 大小:1kb | 下载:0
[数学计算/工程计算] Copy-of-3N
说明:3N+1 The input will consist of a series of pairs of integers i and j, one pair of integers per line. All integers will be less than 1,000,000 and greater than 0. You should process all pairs of integers and for each pair determine the maxim<dj> 在 2025-06-21 上传 | 大小:1kb | 下载:0
[单片机(51,AVR,MSP430等)] HXtoDE_16
说明:Fast 16 bit hex to decimal converter without loop of addition for 8051 platform<mukund> 在 2025-06-21 上传 | 大小:1kb | 下载:0
[单片机(51,AVR,MSP430等)] 3N
说明:3N+1 The input will consist of a series of pairs of integers i and j, one pair of integers per line. All integers will be less than 1,000,000 and greater than 0. You should process all pairs of integers and for each pair determine the maxim<dj> 在 2025-06-21 上传 | 大小:1kb | 下载:0
[单片机(51,AVR,MSP430等)] CRC_16
说明:Modbus CRC calculation software - Can be changed by changing Polynomial.<mukund> 在 2025-06-21 上传 | 大小:1kb | 下载:0
[单片机(51,AVR,MSP430等)] lesson7_4
说明:51单片机向PC发送数据,已调试成功!使用串口软件sscom从51单片机接收或发送数据!-51Microcontroller send data to the PC , has been commissioning success!<陈诚> 在 2025-06-21 上传 | 大小:1kb | 下载:0
[VHDL编程] SRAM_1wait
说明:The aim of this vhdl file is to create a simple interface betwhen the sram and a basic processor on a semisync data bus. This was made using the test board DE2 from Altera.<Hz> 在 2025-06-21 上传 | 大小:1kb | 下载:0
[matlab例程] ADABOOST_te
说明:adaboost 测试,te_func_handle is a handle to the testing function of a learning (weak) algorithm whose prototype is shown below.-te_func_handle is a handle to the testing function of a learning (weak) algorithm whose prototype is shown<raymond> 在 2025-06-21 上传 | 大小:1kb | 下载:0
[matlab例程] threshold_tr
说明: Training of the basic linear classifier where seperation hyperplane is perpedicular to one dimension.<raymond> 在 2025-06-21 上传 | 大小:1kb | 下载:0
[matlab例程] adaboostNewDemo
说明:Creating the training and testing sets<raymond> 在 2025-06-21 上传 | 大小:1kb | 下载:0
[VHDL编程] mo12_counter
说明:基于FPGA的VHDL程序实现模12计数器-FPGA VHDL model12counter<赵静> 在 2025-06-21 上传 | 大小:1kb | 下载:0
[图形图像处理(光照,映射..)] Ratematching
说明:速率匹配 关于LTE中匹配,其中包括子块交织,比特收集,比特选择和修剪-Rate matching on the LTE in the match, including the sub-block interleaving and bit collection, bits and trim options<唐星> 在 2025-06-21 上传 | 大小:1kb | 下载:0