[VHDL编程] move

说明：VGA可移动彩条设计。为了显示更大的图象，用外部ROM取代FPGA的内部ROM-VGA mobile striped design. In order to show more images, with external ROM replace the FPGA internal ROM
<yishuihan> 在 2025-06-26 上传 | 大小：24kb | 下载：0

[VHDL编程] sdram_access

说明：sdram 控制器，VHDL程序源代码。-sdram controller,vhdl program
<wanggt> 在 2025-06-26 上传 | 大小：711kb | 下载：0

[VHDL编程] STM32108PKT-I2C-E2PROM

说明： 本例程使用I2C2 来读写M24C02。 本例程使用校验I2C 总线状态的方式，来使的I2C 器件能可靠通行，然后 再根据I2C 协议，读写M24C02，SysTick 用于通信超时控制。 其中，PB10为I2C2 的时钟脚，PB11为I2C2 的数据脚，都配置为复合 功能开漏输出。 -The routine use I2C2 to read and write M24C02. The routine use check the stat
<zhangxuezhi> 在 2025-06-26 上传 | 大小：29kb | 下载：0

[VHDL编程] SIMPLE-ALU.docx

说明：SIMPLE ALU CODE IN VHDL
<SATYA> 在 2025-06-26 上传 | 大小：169kb | 下载：0

[VHDL编程] spartan_LCD

说明：实现了spartan-3E LCD的显示驱动，可以通过LCD观察数据变化-Realize the Spartan-3 E LCD display driver, can pass LCD observation data changes
<乔子良> 在 2025-06-26 上传 | 大小：1kb | 下载：0

[VHDL编程] I2C_vhdl

说明： IMPORTANT NOTE: This design uses the I2C SCL signal as a clock. This requires that the SCL signal have clean, fast edges on both the rising and falling edges of this signal. Slow rise and fall times on this signal can show noise effects whic
<vijendra pal> 在 2025-06-26 上传 | 大小：830kb | 下载：0

[VHDL编程] manchester_verilog

说明： This design is targeted to the XCR3064XL-7VQ100C CoolRunner CPLD. This is a 3V, 64 macrocell device in a 100 VQFP package. The fitter was allowed to pick the pin-out for the device.
<vijendra pal> 在 2025-06-26 上传 | 大小：10kb | 下载：0

[VHDL编程] manchester_vhdl

说明：This design is targeted to the XCR3064XL-7VQ100C CoolRunner CPLD. This is a 3V, 64 macrocell device in a 100 VQFP package. The fitter was allowed to pick the pin-out for the device.
<vijendra pal> 在 2025-06-26 上传 | 大小：11kb | 下载：0

[VHDL编程] spi_cpld_vhdl

说明：The CoolRunner-II "Confuguring Xilinx FPGAs with SPI Flash Memories using CoolRunner-II CPLDs" reference design is based upon the STMicroelectronics SPI Flash memory M25P20. This design can be easily modified to support other families of S
<vijendra pal> 在 2025-06-26 上传 | 大小：431kb | 下载：0

[VHDL编程] uart_verilog

说明：The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and overrun detection. This design is targeted to the XCR3128XL-7VQ100C CoolRunner CPLD. This
<vijendra pal> 在 2025-06-26 上传 | 大小：5kb | 下载：0

[VHDL编程] uart_vhdl

说明：The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and overrun detection. This design is targeted to the XCR3128XL-7VQ100C CoolRunner CPLD. This
<vijendra pal> 在 2025-06-26 上传 | 大小：6kb | 下载：0

[VHDL编程] smartcard_vhdl

说明：Readme File for Smart Card Reader File Contents ************************************************************************* This zip file contains the following files: -- VHDL Source Files in Smartcard: Top.vhd - top level file for Pic
<vijendra pal> 在 2025-06-26 上传 | 大小：515kb | 下载：0