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[VHDL编程] verilog
说明:本代码设计的是一个通讯系统软件无线电中变换比为5/4的分数倍抽取器,用Verilog编程首先实现4倍内插,再实现5倍抽取。-The code design is a software-defined radio communication system in transformation ratio 5/4 points times the extractor, using Verilog programming the first to achieve four times the inter<张霄> 在 2025-06-19 上传 | 大小:4kb | 下载:0
[VHDL编程] jicunqi
说明:寄存器的VHDL实现,寄存一组二值代码,对寄存器的触发器只要求它们具有置1、置0的功能,在CP正跳沿前接受输入信号,正跳沿时触发翻转,正跳沿后输入即被封锁。-Register VHDL implementation, hosting a group of binary code, on the flip-flop registers only requires that they have set one, set 0 functions in CP are dancing along the<张霄> 在 2025-06-19 上传 | 大小:6kb | 下载:0