资源列表
[VHDL编程] flash_simulation
说明:一个flash控制模块和仿真,内附flash模型-a flash control module and simulation, there are a flash model inside<xin> 在 2025-06-20 上传 | 大小:17kb | 下载:0
[VHDL编程] 4port-sdram
说明:4端口SDRAM控制器verilog程序-4-port SDRAM controller with verilog<xin> 在 2025-06-20 上传 | 大小:28kb | 下载:0
[VHDL编程] Berlekamp_serial
说明:thats the VHDL code for berlekamp serial multiplier<guctiida> 在 2025-06-20 上传 | 大小:270kb | 下载:0
[VHDL编程] berlekamp_parallel
说明:The Berlekamp multiplier [3] uses two basis representations, the polynomial basis for the multiplier and the dual basis for the multiplicand and the product. Because it is normal practice to input all data in the same basis, this means some basis<guctiida> 在 2025-06-20 上传 | 大小:153kb | 下载:0
[VHDL编程] Project-Final-Requirements
说明:that a VHDL code with comparison between CLA and CRA adders modlism project<guctiida> 在 2025-06-20 上传 | 大小:553kb | 下载:0
[VHDL编程] PCI_Verilog
说明:Verilog 实现 PCI 转 LocalBus。已在Quartus 9.0下编译并且上PCBA验证通过。-Verilog achieve PCI to LocalBus. Has been compiled in Quartus 9.0 and verified by the PCBA.<xianwy> 在 2025-06-20 上传 | 大小:16kb | 下载:0
[VHDL编程] DE2_SDCARD
说明:DE2 音频处理 从SD卡读去音乐数据在做相应的处理,通过 音频输出口播放 同事可以从音频输入口加入相应的音乐 也可以从MIK口输入音频-DE2 -DE2 audio processing time from the SD card to do the music data in the processing, I play through the audio output from the audio input of my colleagues to join the music I can<chou> 在 2025-06-20 上传 | 大小:9.42mb | 下载:0