[VHDL编程] ALUALUcontrol

说明：实现32位的ALU，使其能够支持基本的指令。用Verilog HDL语言或VHDL语言来编写，实现ALU及ALU控制器。 -To achieve 32-bit ALU, so that it can support the basic directives. With the Verilog HDL language or VHDL language to write, implement ALU and the ALU controller.
<于伟> 在 2025-12-24 上传 | 大小：1.01mb | 下载：0

[VHDL编程] Move071221133_32

说明：用Verilog HDL语言或VHDL语言来编写，实现32位的桶形移位器。 并在Quartus Ⅱ上实现模拟仿真；-With the Verilog HDL language or VHDL language to write to achieve 32-bit barrel shifter. To achieve in the Quartus Ⅱ simulation
<于伟> 在 2025-12-24 上传 | 大小：799kb | 下载：0

[VHDL编程] VHDL

说明：分频跑马灯数码管示范代码能实现分频跑马灯数码管示范-Crossover Marquee digital control Model Code
<wst> 在 2025-12-24 上传 | 大小：5kb | 下载：0

[VHDL编程] IU3

说明：sun公司的sparc结构之整数处理器vhdl源码-The file is the RTL of the Sparc s integer unit.
<nadir> 在 2025-12-24 上传 | 大小：23kb | 下载：0

[VHDL编程] VERILOG

说明：一本很好的Verilog课件，通俗易懂简单明了适合初学者，给大家分享了~-A very good Verilog courseware, simple easy to understand for beginners, for everyone to share ~
<李振> 在 2025-12-24 上传 | 大小：6.31mb | 下载：0

[VHDL编程] viterbi_for_bch

说明：Viterbi based trellis decoder for (7,4) - binary BCH code-Viterbi based trellis decoder for (7,4)- binary BCH code
<shahifaqeer> 在 2025-12-24 上传 | 大小：1kb | 下载：0

[VHDL编程] RS_decoder

说明：Reed solomon decoder based on table-lookup method VHDL code
<shahifaqeer> 在 2025-12-24 上传 | 大小：4kb | 下载：0

[VHDL编程] wtut_edif

说明：Xilinx clock. DIGITAL CLOCK for Spartan-3 Starter Board. This design shows how to generate a digital clock and display the output to the multiplexed 7- segment display in VHDL.
<shad> 在 2025-12-24 上传 | 大小：20kb | 下载：0

[VHDL编程] wtut_sc

说明：DCM includes a clock delay locked loop used to minimize clock skew for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X devices. DCM synchronizes the clock signal at the feedback clock input (CLKFB) to the clock signal at the input clock
<shad> 在 2025-12-24 上传 | 大小：104kb | 下载：0

[VHDL编程] wtut_ver

说明：DCM supports two frequency modes for the DLL. By default, the DLL_FREQUENCY_MODE attribute is set to Low and the frequency of the clock signal at the CLKIN input must be in the Low (DLL_CLKIN_MIN_LF to DLL_CLKIN_MAX_LF) frequency range (MHz). S
<shad> 在 2025-12-24 上传 | 大小：25kb | 下载：0

[VHDL编程] DFNL

说明：On-chip synchronization is achieved by connecting the CLKFB input to a point on the global clock network driven by a BUFG, a global clock buffer. The BUFG connected to the CLKFB input of the DCM must be sourced from either the CLK0 or CLK2X out
<shad> 在 2025-12-24 上传 | 大小：3kb | 下载：0

[VHDL编程] rs2322

说明：The duty cycle of the CLK0 output is 50-50 unless the DUTY_CYCLE_CORRECTION attribute is set to FALSE, in which case the duty cycle is the same as that of the CLKIN input. The duty cycle of the phase shifted outputs (CLK90, CLK180, and CLK270) is
<shad> 在 2025-12-24 上传 | 大小：1.54mb | 下载：0