资源列表
[VHDL编程] cfft
说明：The FFT architecture is pipelined on a rank basis each rank has its own butterfly and ranks are isolated from each other using memory interleavers.-The FFT architecture is pipelined on a rank basis each rank has its own butterfly and ranks<FPGACore> 在 2025-06-08 上传 | 大小：207kb | 下载：0
[VHDL编程] Twister_DDR_SDRAM_Board_Manual
说明：Twister DDR EP1C6Q240 FPGA 开发板 原理图，PCB,BOM-Twister Board Documentation Schematics, PCB and BOM Rev. B<SEED> 在 2025-06-08 上传 | 大小：1.38mb | 下载：0
[VHDL编程] turbocodes_latest.tar
说明：turbo encode and decoder<suresh> 在 2025-06-08 上传 | 大小：82kb | 下载：0
[VHDL编程] arm9_fpga2_verilog
说明：arm9 FPGA VERILOG 代码-arm9 FPGA VERILOG code<马骥> 在 2025-06-08 上传 | 大小：192kb | 下载：0
[VHDL编程] EnergyEfficientVLSIArchitectureforLinearTurboEqua
说明：Energy efficient for turbo encoder decoder<suresh> 在 2025-06-08 上传 | 大小：524kb | 下载：0
[VHDL编程] IterativeDecodingofBinary
说明：In this paper, energy efficient VLSI architectures for linear turbo equalization are studied. Linear turbo equalizers exhibit dramatic bit error rate (BER) improvement over conventional equalizers by enabling a form of joint equalization and deco<suresh> 在 2025-06-08 上传 | 大小：1.45mb | 下载：0
[VHDL编程] MapAlgorithm
说明：However, turbo equalizers can be computationally complex and hence require significant power consumption. In this paper, we present an energy-efficient VLSI architecture for such linear turbo equalizers. Key architectural techniques include elimi<suresh> 在 2025-06-08 上传 | 大小：1.25mb | 下载：0
[VHDL编程] RECURSIVEALGORITHMFOREFFICIENTMAPDECODING
说明：Early termination enables powering down parts of the soft-input soft-output (SISO) equalizer and decoder thereby saving power.<suresh> 在 2025-06-08 上传 | 大小：102kb | 下载：0
[VHDL编程] VerilogLangRefManual
说明：Simulation results show that energy savings in the range 30–60 and 10–60 are achieved in equalization and decoding, respectively. Furthermore, we present finite precision requirements of the linear turbo equalizer and an efficient rescaling metho<suresh> 在 2025-06-08 上传 | 大小：1.22mb | 下载：0