资源列表
[VHDL编程] MAX263-MAX268
说明：D板的数字可编程有源滤波模块设计，MAX26 系列数字编码式滤波器的使用方法-MAX263，MAX264，MAX265，MAX266，MAX267，MAX268<雪域高原> 在 2025-06-09 上传 | 大小：3.93mb | 下载：0
[VHDL编程] fallthrough_small_fifo_v2
说明：同步fifo设计，仿真已通过，用Verilog编写，代码短小-Synchronous fifo design, simulation has been adopted, written with Verilog, code short<xinghuo> 在 2025-06-09 上传 | 大小：1kb | 下载：0
[VHDL编程] small_fifo
说明：同步fifo设计，仿真已通过，用Verilog编写，代码短小，易懂-Synchronous fifo design, simulation has been adopted, written with Verilog, code short and easy to understand<xinghuo> 在 2025-06-09 上传 | 大小：1kb | 下载：0
[VHDL编程] modelsim6.0
说明：modelsim 中文使用手册，希望对想学习mldelsim的人有用-modelsim Chinese user manual, and they hope people who want to learn a useful mldelsim<xinghuo> 在 2025-06-09 上传 | 大小：379kb | 下载：0
[VHDL编程] cFFT
说明：CFFT is a radix-4 fast Fourier transform (FFT) core with configurable data width and a configurable number of sample points in the FFT. Twiddle factors are implemented using the CORDIC algorithm, causing the gain of the CFFT core to be differen<Nagendran> 在 2025-06-09 上传 | 大小：179kb | 下载：0
[VHDL编程] viterbi
说明：This a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is w<Nagendran> 在 2025-06-09 上传 | 大小：639kb | 下载：0
[VHDL编程] lowpowerfir
说明：This project was undertaken to produce a low power FIR filter for inclusion in a VHDL target library. The design was completed using OrCAD s Capture CIS, from this the VHDL code has been extracted. This method has allowed complete testing of the syst<Nagendran> 在 2025-06-09 上传 | 大小：437kb | 下载：0
[VHDL编程] spacewar_final
说明：一款用VHDL编写的飞机大战游戏很好很实用-a game by VHDL<Donghf> 在 2025-06-09 上传 | 大小：2.93mb | 下载：0