[VHDL编程] hdlc_decode

说明：基于Verilog的HDLC解码器。其中时钟的提取采用数字锁相环-The HDLC decoder based on Verilog. Which are extracted using digital phase-locked loop clock
<栾帅> 在 2025-06-09 上传 | 大小：2.59mb | 下载：0

[VHDL编程] hdlc_encode

说明：基于Verilog的HDLC解码器。输出外接485进行差分输出。-HDLC-based Verilog decoder. Output of an external differential output 485.
<栾帅> 在 2025-06-09 上传 | 大小：4.41mb | 下载：0

[VHDL编程] hdlc_7960

说明：基于Verilog的7960实现。主要实现曼彻斯特的编解码。采用的倍频采样的方法。-Based on the 7960 Verilog implementation. Main achieved Manchester encoding and decoding. Frequency sampling method used.
<栾帅> 在 2025-06-09 上传 | 大小：686kb | 下载：0

[VHDL编程] vhdlsvm

说明：这是用vhdl 编写的UART控制程序，已经通过测试-UART的完整源代码.-It is written in vhdl UART control program has been tested-UART complete source code.
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[VHDL编程] gray

说明：基于Verilog的GRAY计数器。以及测试文件，在simulation的文件件中的top文件。-Based on Verilog, GRAY counter. And test files, the files in the simulation of the top pieces of the file.
<栾帅> 在 2025-06-09 上传 | 大小：2.31mb | 下载：0

[VHDL编程] 38018066-VHDL

说明：INTRODUCTION § The VHSIC Hardware Descr iption Language (VHDL) is an industry standard language used to describe hardware from the abstract to concrete level. § The language not only defines the syntax but also defines very clear simulation
<phitoan> 在 2025-06-09 上传 | 大小：125kb | 下载：0

[VHDL编程] 50973937-VHDL-Report

说明：Introduction This report is organized as following.First, it is divided into chapter 2 to chapter 12. Within each chapter, VHDL code is presented at the beginning of each problem. Then, simulation results for these codes is also included. For s
<phitoan> 在 2025-06-09 上传 | 大小：993kb | 下载：0

[VHDL编程] 34105908-Multipliers-Using-Vhdl

说明：ABSTRACT: Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. However, area and
<phitoan> 在 2025-06-09 上传 | 大小：371kb | 下载：0

[VHDL编程] 38504873-pll

说明：Introduction In 2004 Octavian Florescu created the UW ASIC group. At that time, the analog subgroup of the UW ASIC group was involved in the design of a PLL. The topology of that PLL, which is now referred to as Phase Locked Loop Version 1, i
<phitoan> 在 2025-06-09 上传 | 大小：358kb | 下载：0

[VHDL编程] 40716003-VHDL

说明：What is VHDL? • VHDL stands for VHSIC Hardware Descr iption Language. • VHSIC is an abbreviation for Very High Speed Integrated Circuit, a project sponsered by the US Government and Air Force begun in 1980 to advance techniques
<phitoan> 在 2025-06-09 上传 | 大小：86kb | 下载：0

[VHDL编程] 44317447-Vhdl-Sim-Syn

说明：This document is meant to be an introduction to VHDL both as a simulation language and an input language for automatic logic synthesis. It is based on material originally prepared for the ASIC Design Laboratory taught at the University of Twente
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[VHDL编程] hidoh

说明：汇编计数器，可以在计算机上直接运行的软件程序-Compilation of the counter, you can run directly on a computer software program
<shjt> 在 2025-06-09 上传 | 大小：6kb | 下载：0