[VHDL编程] Avalon_VGA

说明：Avalon_VGA，-- This design provides an interface to the Alcahest VGA daughter card. -- The design comprises of an 8-bit VGA driver with Avalon bus interfaces. There are a total of -- three Avalon interfaces.-Avalon_VGA.-- This design provides an i
<陈朋> 在 2025-06-19 上传 | 大小：16kb | 下载：0

[VHDL编程] xapp616

说明：A Huffman implementation reference design in both VHDL and Verilog is provided by the Xilinx-A. Huffman implementation reference desig n in both VHDL and Verilog is provided by the Xili nx
<> 在 2025-06-19 上传 | 大小：13kb | 下载：0

[VHDL编程] yimazhenque

说明：47译码器器的verilog源代码,经过编译仿真的，绝对真确，对初学者很有帮助-47 decoder for verilog source code, compiled simulation, absolute authenticity, helpful for beginners
<刘东辉> 在 2025-06-19 上传 | 大小：21kb | 下载：0

[VHDL编程] lpm_mul

说明：８＊８的乘法器verilog源代码,经过编译仿真的，绝对真确，对初学者很有帮助-8* 8 Multiplier verilog source code, compiled simulation, absolute authenticity, helpful for beginners
<刘东辉> 在 2025-06-19 上传 | 大小：27kb | 下载：0

[VHDL编程] binary2bcd

说明：This build is for developing a "binary-to-BCD" converter for use in // displaying numerals in base-10 so that people can read and interpret the // numbers more readily than they could if the numbers were displayed in // binary or hexadecimal fo
<陈朋> 在 2025-06-19 上传 | 大小：41kb | 下载：0

[VHDL编程] DaFilter

说明：/* This program generates the DApkg.vhd file that is used to define * the DA filter core and gives its parameters and the contents of the * Distributed Arithmetic Look-up-table "DALUT" according to the DA algorithm-/* This program generates t
<陈朋> 在 2025-06-19 上传 | 大小：15kb | 下载：0

[VHDL编程] DCT_vhdl

说明：IDCT-M is a medium speed 1D IDCT core -- it can accept a continous stream of 12-bit input words at a rate of -- 1 bit/ck cycle, operating at 50MHz speed, it can process MP@ML MPEG video -- the core is 100％ synthesizable-IDCT-M is a medium speed
<陈朋> 在 2025-06-19 上传 | 大小：10kb | 下载：0

[VHDL编程] Shifters_vhdl

说明：-- Title : Barrel Shifter (Pure combinational) -- This VHDL design file is an open design you can redistribute it and/or -- modify it and/or implement it after contacting the author -- You can check the draft license at --- Title : Barrel Shift
<陈朋> 在 2025-06-19 上传 | 大小：2kb | 下载：0

[VHDL编程] cf_interleaver2

说明：interleaver即交织器，里面包含有C,VHDL,VRILOG HDL三种语言写的交织器, 包括各种各样的组合达六七十种，描写详尽，是一个难得的学习交织器的材料 -interleaver that interleaver, which contains C, VHDL, VRILOG HDL three languages to write the interleaver, including a variety of combinations to depend species,
<陈朋> 在 2025-06-19 上传 | 大小：352kb | 下载：0

[VHDL编程] mdct.tar

说明：这是06年4月刚刚完成的程序，从opencore.org下载而来。用vhdl语言描写，以及matlab仿真，testbench，以及在xinlinx上的综合。 The MDCT core is two dimensional discrete cosine transform implementation designed for use in compression systems like JPEG. Architecture is based on parallel distribut
<陈朋> 在 2025-06-19 上传 | 大小：1.69mb | 下载：0

[VHDL编程] fpu_v18

说明：<Floating Point Unit Core> fpupack.vhd pre_norm_addsub.vhd addsub_28.vhd post_norm_addsub.vhd pre_norm_mul.vhd mul_24.vhd vcom serial_mul.vhd post_norm_mul.vhd pre_norm_div.vhd serial_div.vhd post_norm_div.vhd pre_norm_s
<陈朋> 在 2025-06-19 上传 | 大小：466kb | 下载：0

[VHDL编程] System09

说明：BurchED B5-X300 Spartan2e using XC2S300e device Top level file for 6809 compatible system on a chip Designed with Xilinx XC2S300e Spartan 2+ FPGA. Implemented With BurchED B5-X300 FPGA board, B5-SRAM module, B5-CF module and B5-FPGA-CPU-IO
<陈朋> 在 2025-06-19 上传 | 大小：596kb | 下载：0