资源列表
[VHDL编程] verilog-example
说明:verilog实例,是开发cpld、fpga时参考程序,很实用-Verilog example, is the development of CPLD, FPGA reference procedures, it is practical<li> 在 2025-06-11 上传 | 大小:111kb | 下载:0
[VHDL编程] 5589e6b62fd6
说明:doc vhdl to design a pwm signal to controling a C- C motor this doc is tested and was given good results-doc vhdl to design a pwm signal to controling a C- C motor this doc is tested and was given good results<skan> 在 2025-06-11 上传 | 大小:723kb | 下载:0
[VHDL编程] Process-P-FPGA_1
说明:this document contain many search papers wich descrid the system Process trainer PT326 and the control method of systems using FPGA<skan> 在 2025-06-11 上传 | 大小:4.33mb | 下载:0
[VHDL编程] Process_-FPGA_2
说明:this document contain many methods of controling a process using fpga, the major exempl is the process trainer pt326<skan> 在 2025-06-11 上传 | 大小:16.13mb | 下载:0
[VHDL编程] mode1_master
说明:UART0 模式1主机程序TX0线为P0.0,RX0线为P0.1,TX0采用T2为波特率产生源,RX0采用T1为波特率产生源-UART0 mode, a host program TX0 line for the P0.0, the RX0 line for P0.1 obtained, TX0 as using T2 generation source for the baud rate, RX0 uses T1 for baud rate generator source<静儿> 在 2025-06-11 上传 | 大小:1kb | 下载:0
[VHDL编程] Mux
说明:designing of multiplexer using vhdl language<sriramgopal> 在 2025-06-11 上传 | 大小:1kb | 下载:0
[VHDL编程] RS232-bus-protocol
说明:有fpga VHDL原程序 锁脚文件 及下载文件 ,及uart通信协议-Fpga the VHDL program locks the foot of the original files and download files, and uart communication protocol<吴信松> 在 2025-06-11 上传 | 大小:338kb | 下载:0
[VHDL编程] BaudRate_VHDL
说明:Many frequency generator, any baud rate generator<浪子> 在 2025-06-11 上传 | 大小:57kb | 下载:0