资源列表
[VHDL编程] divider
说明：使用模为2N+1的计数器,让输出时钟在X-1(X在0到2N-1之间)和2N时各翻转一次,则可得到奇数分频器,但是占空比并不是50 -The use of modulo 2N+1 counter, let the output clock in the X-1 (X between 0 and 2N-1) and 2N of the turning once, then can get the odd divider, but the duty ratio is not 50<houxili> 在 2025-06-19 上传 | 大小：1kb | 下载：0
[VHDL编程] DDS-MY-WORK-1
说明：FPGA模拟数字信号发生器DDS verilog-FPGA analog and digital signal generator DDS verilog<luowang> 在 2025-06-19 上传 | 大小：10.19mb | 下载：0
[VHDL编程] displayCounter2.tar
说明：Verilog example of a program that uses a 7 segment display (included in fpga) to display a counter 0 to 99. Implemmented in FPGA Nexys3-Verilog example of a program that uses a 7 segment display (included in fpga) to display a counter 0 to 99. Imple<yunacu> 在 2025-06-19 上传 | 大小：8kb | 下载：0
[VHDL编程] inputPinsTest.tar
说明：Verilog example of a program that test the input and outputs pins FPGA by making them 1 and 0 in a specific time. Implemmented in FPGA Nexys3-Verilog example of a program that test the input and outputs pins FPGA by making them 1 and 0 in a specific<yunacu> 在 2025-06-19 上传 | 大小：77kb | 下载：0
[VHDL编程] hcsr04.tar
说明：Verilog program of the interface between a FPGA and the HCSR04 arduino sensor displaying the distance measured in the 7 segment display. Implemmented in FPGA Nexys3<yunacu> 在 2025-06-19 上传 | 大小：934kb | 下载：0
[VHDL编程] UsbFPGAdemo
说明：FPGA底层的USB接口芯片的驱动，用于向上位机传送数据。-Driving USB interface chip FPGA bottom, used to transmit data to the host computer.<张仰望> 在 2025-06-19 上传 | 大小：2.09mb | 下载：0