资源列表
[VHDL编程] pararel-8-bit-adder-verilog
说明:implementation of 8bit adder with pararel computation. It s use S/P converter and P/S converter. The code is written in verilog language<appolo> 在 2025-06-20 上传 | 大小:1kb | 下载:0
[VHDL编程] serial-cordic-verilog
说明:implementation of cordic algorithm for many aplication like cos, sinus, polar to rectangular conversion and rectangular to polar conversion. It s written in verilog language and testbench is included<appolo> 在 2025-06-20 上传 | 大小:3kb | 下载:0
[VHDL编程] DDS
说明:基于FPGA的数字信号合成器(DDS),采用VHDL语言编写,能够实现正弦波、三角波、方波、锯齿波这四种波形的产生。 提示:最后输出的模块是串行DA,可根据具体情况更改驱动。-Digital synthesizer (DDS) based on FPGA, using VHDL language, to achieve sine wave, triangle wave, square wave, sawtooth waveform generation four. Tip: The la<康二栋> 在 2025-06-20 上传 | 大小:2.67mb | 下载:0
[VHDL编程] sine-wave-generate
说明:Sine wave Generator using the direct digital synthesis Method<rss.nitk> 在 2025-06-20 上传 | 大小:153kb | 下载:0