[VHDL编程] top

说明：FPGA开发UART软件有一定的参考价值，请参考该软件进行编译Altera软件编写的-FPGA development software UART has some reference value, refer to the software to compile software written Altera
<whq> 在 2025-06-21 上传 | 大小：2.63mb | 下载：0

[VHDL编程] lpf

说明：利用altera的IP核构建的并行数字滤波器，实现100kHZ低通，带外抑制40dB-Altera use IP cores constructed parallel digital filters achieve 100kHZ low pass, band rejection of 40dB
<周正坤> 在 2025-06-21 上传 | 大小：13.03mb | 下载：0

[VHDL编程] uart_ram

说明：串口接收数据校样后存入双口ram,接收完整帧数据后，置中断，通知串口发送-After receiving proof serial data stored in dual port ram, receive a complete fr a me of data after the interrupt, serial port to send notifications
<yxs> 在 2025-06-21 上传 | 大小：4.17mb | 下载：0

[VHDL编程] ieep1.3

说明：10-b 50-MHz digital-to-analog (D/A) converter is presented which is based on a dual-ladder resistor string. This approach allows the linearity requirements to be met without the need for selection or trimming. The D/A decoding scheme reduces th
<john> 在 2025-06-21 上传 | 大小：495kb | 下载：0

[VHDL编程] ieep1.4

说明：10-b binary-weighted D/A converter based on current division is presented. The effective resolution bandwidth is 5 MHz at a maximum clock frequency of 40 MHz. The circuit is integrated in a 0.8-pm double-metal CMOS technology and the chip are
<john> 在 2025-06-21 上传 | 大小：488kb | 下载：0

[VHDL编程] ieep1.5

说明：This paper describes a 10-b high-speed COMS DAC fabricated by 0.8-pm double-poly double-metal CMOS technology. In the DAC, a new current source called the thresholdvoltage compensated current source is used in the two-stage current array to r
<john> 在 2025-06-21 上传 | 大小：578kb | 下载：0

[VHDL编程] ieep1.6

说明：low-power 16-bit CMOS D/A converter for portable digital audio is described. The converter is based on current division. To guarantee monotonicity and a good small-signal reproduction, a dynamic segmentation technique is used. A geometric avera
<john> 在 2025-06-21 上传 | 大小：624kb | 下载：0

[VHDL编程] morsecode

说明：用DE2板，用SW0 到1表示想要的字母，KEY1运行，红灯显示对应的摩斯码，KEY0重置-With DE2 board with SW0 to 1 indicates the desired letter, KEY1 running red lights display the corresponding Morse code, KEY0 reset
<何亦嘉> 在 2025-06-21 上传 | 大小：1kb | 下载：0

[VHDL编程] vga_adapter

说明：可以用这个来把想要显示的图像显示在显示屏上。也可以用来做动画（画一帧擦一帧再移动再画）-You can use this to display the image you want to display on the screen. Can also be used to make the animation (painting a rub a painting and then move again)
<何亦嘉> 在 2025-06-21 上传 | 大小：12kb | 下载：0

[VHDL编程] MMUMPU

说明：qsys with mmu mpu. Design in SOPC quartus 9.0
<jcc18> 在 2025-06-21 上传 | 大小：13.92mb | 下载：0

[VHDL编程] wave_gen_vhd_s6

说明：波形发生器，可以产生需要的波形，根据你的需要改变波的频率或者其他参数-as the same as its name
<郑岩> 在 2025-06-21 上传 | 大小：1.83mb | 下载：0

[VHDL编程] clock

说明：采用可综合的Verilog代码编写一个带闹钟功能的数字钟。使其具有以下功能： 1)计时功能：包括小时、分钟、秒钟。 2)校时功能：对小时、分钟和秒钟进行手动校时。 3)定时和闹钟功能：能在手工设定的时间产生闹铃音。 -Using synthesizable Verilog coding a digital clock with alarm. It has the following features: 1) timing functions include: hours, m
<shikai> 在 2025-06-21 上传 | 大小：2kb | 下载：0