资源列表
[VHDL编程] multi_bank_OLD
说明:A expensive MultiBank Algorithm for DVB Deinterleaving<kalidas> 在 2025-06-09 上传 | 大小:54kb | 下载:0
[VHDL编程] ep2c35_4_11_spi_send
说明:这个程序用来在FPGA内实现SPI接口的通讯。程序使用verilog硬件语言编写。-this program is writen by verilog HDL.it is for spi communicate in FPGA<Nevin Young> 在 2025-06-09 上传 | 大小:54kb | 下载:0
[VHDL编程] RC6-block-cipher-using-VHDL
说明:VHDL implementation of RC6 encryption algorithm Test file represent applying all zero input and all zero key note that result is correct but bytes positions are swapped<waleed> 在 2025-06-09 上传 | 大小:54kb | 下载:0
[VHDL编程] PWM
说明:在一般MCU都没有自带PWM模块,必须通过定时器产生。虽然能够实现这个PWM,但是需要以浪费宝贵的定时器为前提。本例采用STC12C些列单片机的两路PWM模块产生两路PWM,占空比从0 --99 -In general, do not bring their own low-end MCU PWM module, must be the timer. Although able to achieve this PWM, but need to waste valuable timer as a<linjian> 在 2025-06-09 上传 | 大小:54kb | 下载:0
[VHDL编程] digtal_clock
说明:基于fpga的数字钟, quartus II 环境-digtal clock implement on fpga<mend> 在 2025-06-09 上传 | 大小:54kb | 下载:0
[VHDL编程] add_unsigned1
说明:Adding Unsigned Numbers. Introduction. Adding numbers in binary is pretty much the same as adding in base ten. In fact, you could argue that it s even easier<omid> 在 2025-06-09 上传 | 大小:54kb | 下载:0
[VHDL编程] quick_reference
说明:SPECMAN LEARNING MATERIAL FOR VERIFICATION OF VHDL VERILOG SOC<ABRAXAS> 在 2025-06-09 上传 | 大小:54kb | 下载:0
[VHDL编程] UARTNUMBER
说明:通过通讯控制数码管显示。以成功应用到项目中。通过S7200的自由协议发送要显示的数据到单片机中来控制4位数码管的显示。-Through the communication control digital tube display. With the successful application to the project. Through the S7200 free protocol to send data to be displayed to the MCU to control the<wym> 在 2025-06-09 上传 | 大小:54kb | 下载:0