资源列表
[VHDL编程] FPGA_design_of_the_impact_factor_of_the_clock
说明:影响FPGA设计中时钟因素的探讨,能帮组FPGA的设计-FPGA design of the impact factor of the clock,and can help the FPGA design<lengkongqi> 在 2025-06-08 上传 | 大小:516kb | 下载:0
[VHDL编程] Spartan3VGATest
说明:This VGA test will draw a single color page and change color every one second. VGA resolution is 640x480 @25 MHZ 8 colors<Kosta > 在 2025-06-08 上传 | 大小:516kb | 下载:0
[VHDL编程] washmachine
说明:源码为洗衣机控制电路的Verilog代码实现,分六个模块实现,顶层模块有原理图实现-this code is for the control_circuit of machine in Verilog ,it is divided into six modules, the top-level is schematic<邓广兴> 在 2025-06-08 上传 | 大小:516kb | 下载:0
[VHDL编程] Adder_Kogge_Stone_32bit_With_Test_Bench
说明:verilog source code and test bench of Adder Kogge Stone 32-Bit<abanuaji> 在 2025-06-08 上传 | 大小:516kb | 下载:0
[VHDL编程] HOWPTOPUSEPSDRAM
说明:关于SDRAM的用法,看看有用的SDRAMSDRAM-About SDRAM usage, see useful<zhaotao> 在 2025-06-08 上传 | 大小:516kb | 下载:0
[VHDL编程] lab4
说明:s the design and simulation of a simple traffic light controller: The controller consists of a clock divider block, two sequential circuits: a timing counter and a signal generator (state generator), and a decoder. The counter is used to define a<titorgtfo> 在 2025-06-08 上传 | 大小:517kb | 下载:0
[VHDL编程] PWM-VHDL
说明:是使用VHDL编写的一段PWM产生程序,里面附带了详细的说明和源程序。-Is to use VHDL to write a PWM generation procedure, it comes with detailed instructions and the source program.<qu xiansheng> 在 2025-06-08 上传 | 大小:517kb | 下载:0