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[VHDL编程] JDL12864LCD
说明:基于Actel A3P030 FPGA,液晶采用JDL12864串行接口,时钟48MHz-Based on Actel A3P030 FPGA, LCD using JDL12864 serial interface, clock 48MHz<songxin> 在 2025-12-23 上传 | 大小:4kb | 下载:0
[VHDL编程] WIRELESS
说明:This file contains source code for DS-CDMA transciver using VHDL. it is having two source codes one is for Transmitter and another is for reciever programme.<RUPA KRISHNA> 在 2025-12-23 上传 | 大小:4kb | 下载:0