[VHDL编程] viterbi_for_bch

说明：Viterbi based trellis decoder for (7,4) - binary BCH code-Viterbi based trellis decoder for (7,4)- binary BCH code
<shahifaqeer> 在 2025-06-09 上传 | 大小：1kb | 下载：0

[VHDL编程] RS_decoder

说明：Reed solomon decoder based on table-lookup method VHDL code
<shahifaqeer> 在 2025-06-09 上传 | 大小：4kb | 下载：0

[VHDL编程] wtut_edif

说明：Xilinx clock. DIGITAL CLOCK for Spartan-3 Starter Board. This design shows how to generate a digital clock and display the output to the multiplexed 7- segment display in VHDL.
<shad> 在 2025-06-09 上传 | 大小：20kb | 下载：0

[VHDL编程] wtut_sc

说明：DCM includes a clock delay locked loop used to minimize clock skew for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X devices. DCM synchronizes the clock signal at the feedback clock input (CLKFB) to the clock signal at the input clock
<shad> 在 2025-06-09 上传 | 大小：104kb | 下载：0

[VHDL编程] wtut_ver

说明：DCM supports two frequency modes for the DLL. By default, the DLL_FREQUENCY_MODE attribute is set to Low and the frequency of the clock signal at the CLKIN input must be in the Low (DLL_CLKIN_MIN_LF to DLL_CLKIN_MAX_LF) frequency range (MHz). S
<shad> 在 2025-06-09 上传 | 大小：25kb | 下载：0

[VHDL编程] wtut_vhd

说明：When the DLL_FREQUENCY_MODE attribute is set to High, the frequency of the clock signal at the CLKIN input must be in the High (DLL_CLKIN_MIN_HF to DLL_CLKIN_MAX_HF) frequency range (MHz). See The Programmable Logic Data Book for the current DL
<shad> 在 2025-06-09 上传 | 大小：35kb | 下载：1

[VHDL编程] DFNL

说明：On-chip synchronization is achieved by connecting the CLKFB input to a point on the global clock network driven by a BUFG, a global clock buffer. The BUFG connected to the CLKFB input of the DCM must be sourced from either the CLK0 or CLK2X out
<shad> 在 2025-06-09 上传 | 大小：3kb | 下载：0

[VHDL编程] rs2322

说明：The duty cycle of the CLK0 output is 50-50 unless the DUTY_CYCLE_CORRECTION attribute is set to FALSE, in which case the duty cycle is the same as that of the CLKIN input. The duty cycle of the phase shifted outputs (CLK90, CLK180, and CLK270) is
<shad> 在 2025-06-09 上传 | 大小：1.54mb | 下载：0

[VHDL编程] VHDL_flash

说明：vhdl chip design a very good design
<Vampiro> 在 2025-06-09 上传 | 大小：4.6mb | 下载：0

[VHDL编程] VHDL_Codes

说明：vhdl codes of basic components
<Vampiro> 在 2025-06-09 上传 | 大小：3.58mb | 下载：0

[VHDL编程] 111

说明：Verilog语言编写的循环彩灯控制器 这个程序我已经在Actel板上烧过了，没问题。如果还有什么问题应该是你的板不同或者工具不同，我是在libero_8.5上做的 -VeriloG HDL IS VEVRY USEFUL
<xinran> 在 2025-06-09 上传 | 大小：4kb | 下载：0

[VHDL编程] Shortest_job_first

说明：短作业优先级算法（在VS2005中，可以自己创建各进程的运行时间，导入后能够运行，）-shortest job first（）
<qin yali> 在 2025-06-09 上传 | 大小：365kb | 下载：0