资源列表
[VHDL编程] fir_test01
说明:在quartus ii 环境下,用VHDL语言编写的基于ALTERA 的IP核的FIR低通滤波器。 -In quartus ii environment, using VHDL language ALTERA FIR IP core based on the low-pass filter.<xuegamgma> 在 2025-06-22 上传 | 大小:1.44mb | 下载:0
[VHDL编程] fec_encoder
说明:This module Implements the Forward Error Correction Encoder<ashwanth> 在 2025-06-22 上传 | 大小:2kb | 下载:0
[VHDL编程] carry-look-ahead-adder32
说明:This implements Carry look ahead adder in verilog<ashwanth> 在 2025-06-22 上传 | 大小:1kb | 下载:0
[VHDL编程] wallace_tree_multiplier
说明:this implements wallace tree multiplier in verilog<ashwanth> 在 2025-06-22 上传 | 大小:3kb | 下载:0
[VHDL编程] New-folder
说明:i have attached area efficient and low power carry select adder and with code<bhuvaneshwari> 在 2025-06-22 上传 | 大小:197kb | 下载:0
[VHDL编程] image-new
说明:this coding is very effectively used for the image compression technique in vhdl<bhuvaneshwari> 在 2025-06-22 上传 | 大小:608kb | 下载:0
[VHDL编程] Verilog-Accumulator
说明:the folder contains two files written by Verilog HDL. the first one is an implementation of an accumulator that takes serial data as an input, and its output will be an accumulated sum of each consecutive four input samples. the second file is a te<sawsan> 在 2025-06-22 上传 | 大小:1kb | 下载:0
[VHDL编程] booth_mul
说明:Booth multiplier used for multiplication of 2 s complement numbers in digital design by using booth multiplier we can reduce the partial products by encoding bits in the multiplier and perform the operation according to the encoded results on multipl<abhinay> 在 2025-06-22 上传 | 大小:1kb | 下载:0
[VHDL编程] Crack_QII_13.1_Windows
说明:quartus 13.1 的破解文件 最新版本的破解文件-quartus 13.1 crack file latest version of the crack file<沧海> 在 2025-06-22 上传 | 大小:27kb | 下载:0