文件名称:pn_code
介绍说明－－下载内容均来自于网络，请自行研究使用
系数为4的扰码生成器，并每四位扰码产生一个触发串并转换的触发信号，可用于4b/5b编码的触发信号。verilog程序，带test程序-coefficient of the four scrambler generator, and every four scrambler have triggered a string conversion and the trigger signal can be used to trigger 4b/5b coding signal. Verilog procedures, with test procedures
(系统自动生成,下载前可以参看下载内容)
下载文件列表
pn_code
.......\automake.log
.......\coregen.log
.......\coregen.prj
.......\pn_code.dhp
.......\pn_code.npl
.......\pn_code.v
.......\pn_code_test.v
.......\pn_encode.cmd_log
.......\pn_encode.lso
.......\pn_encode.ngc
.......\pn_encode.ngr
.......\pn_encode.prj
.......\pn_encode.stx
.......\pn_encode.syr
.......\pn_encode_pn_code_test_v_tf.fdo
.......\pn_encode_pn_code_test_v_tf.udo
.......\pn_encode_vhdl.prj
.......\transcript
.......\vsim.wlf
.......\work
.......\....\glbl
.......\....\....\verilog.psm
.......\....\....\_primary.dat
.......\....\....\_primary.vhd
.......\....\pn_encode
.......\....\.........\verilog.psm
.......\....\.........\_primary.dat
.......\....\.........\_primary.vhd
.......\....\pn_encode_pn_code_test_v_tf
.......\....\...........................\verilog.psm
.......\....\...........................\_primary.dat
.......\....\...........................\_primary.vhd
.......\....\_info
.......\xst
.......\...\work
.......\...\....\hdllib.ref
.......\...\....\vlg1B
.......\...\....\.....\pn_encode.bin
.......\__projnav
.......\.........\coregen.rsp
.......\.........\createTF.err
.......\.........\pn_code.gfl
.......\.........\pn_code_flowplus.gfl
.......\.........\pn_encode.xst
.......\.........\runXst_tcl.rsp
.......\__projnav.log
.......\automake.log
.......\coregen.log
.......\coregen.prj
.......\pn_code.dhp
.......\pn_code.npl
.......\pn_code.v
.......\pn_code_test.v
.......\pn_encode.cmd_log
.......\pn_encode.lso
.......\pn_encode.ngc
.......\pn_encode.ngr
.......\pn_encode.prj
.......\pn_encode.stx
.......\pn_encode.syr
.......\pn_encode_pn_code_test_v_tf.fdo
.......\pn_encode_pn_code_test_v_tf.udo
.......\pn_encode_vhdl.prj
.......\transcript
.......\vsim.wlf
.......\work
.......\....\glbl
.......\....\....\verilog.psm
.......\....\....\_primary.dat
.......\....\....\_primary.vhd
.......\....\pn_encode
.......\....\.........\verilog.psm
.......\....\.........\_primary.dat
.......\....\.........\_primary.vhd
.......\....\pn_encode_pn_code_test_v_tf
.......\....\...........................\verilog.psm
.......\....\...........................\_primary.dat
.......\....\...........................\_primary.vhd
.......\....\_info
.......\xst
.......\...\work
.......\...\....\hdllib.ref
.......\...\....\vlg1B
.......\...\....\.....\pn_encode.bin
.......\__projnav
.......\.........\coregen.rsp
.......\.........\createTF.err
.......\.........\pn_code.gfl
.......\.........\pn_code_flowplus.gfl
.......\.........\pn_encode.xst
.......\.........\runXst_tcl.rsp
.......\__projnav.log