文件名称:BFSK_VHDL_CODING
介绍说明－－下载内容均来自于网络，请自行研究使用
使用DDS技术，应用altera公司的芯片，以及杭州康芯公司的试验箱，实现BFSK信号的调制解调-The use of DDS technology, applications altera chips, as well as the core company in Hangzhou, Culture and Sport chamber, the realization of BFSK signal modulation and demodulation
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下载文件列表
fsk
...\ADDER10B.VHD
...\ADDER32B.VHD
...\adder7b.vhd
...\cmp_state.ini
...\db
...\..\altsyncram_0sj2.tdf
...\..\altsyncram_5mp.tdf
...\..\altsyncram_6v51.tdf
...\..\altsyncram_hq21.tdf
...\..\dds.asm.qmsg
...\..\dds.cbx.xml
...\..\dds.cmp.cdb
...\..\dds.cmp.hdb
...\..\dds.cmp.kpt
...\..\dds.cmp.logdb
...\..\dds.cmp.rdb
...\..\dds.cmp.tdb
...\..\dds.cmp0.ddb
...\..\dds.dbp
...\..\dds.db_info
...\..\dds.eco.cdb
...\..\dds.eds_overflow
...\..\dds.fit.qmsg
...\..\dds.hier_info
...\..\dds.hif
...\..\dds.map.cdb
...\..\dds.map.hdb
...\..\dds.map.logdb
...\..\dds.map.qmsg
...\..\dds.pre_map.cdb
...\..\dds.pre_map.hdb
...\..\dds.psp
...\..\dds.pss
...\..\dds.rtlv.hdb
...\..\dds.rtlv_sg.cdb
...\..\dds.rtlv_sg_swap.cdb
...\..\dds.sgdiff.cdb
...\..\dds.sgdiff.hdb
...\..\dds.signalprobe.cdb
...\..\dds.sim.hdb
...\..\dds.sim.qmsg
...\..\dds.sim.rdb
...\..\dds.sim.vwf
...\..\dds.sld_design_entry.sci
...\..\dds.sld_design_entry_dsc.sci
...\..\dds.syn_hier_info
...\..\dds.tan.qmsg
...\..\dds_cmp.qrpt
...\..\dds_sim.qrpt
...\..\decode_ogi.tdf
...\..\wed.zsf
...\dds.asm.rpt
...\dds.cdf
...\dds.done
...\dds.fit.eqn
...\dds.fit.rpt
...\dds.fit.smsg
...\dds.fit.summary
...\dds.flow.rpt
...\dds.map.eqn
...\dds.map.rpt
...\dds.map.summary
...\dds.pin
...\dds.pof
...\dds.qpf
...\dds.qsf
...\dds.qws
...\dds.sim.rpt
...\dds.sof
...\dds.tan.rpt
...\dds.tan.summary
...\DDS.VHD
...\dds.vwf
...\dds_assignment_defaults.qdf
...\fsk_decode.vhd
...\LUT10X10.MIF
...\ps7.vhd
...\REG10B.VHD
...\REG32B.VHD
...\reg7b.vhd
...\sin7.mif
...\SIN_ROM.VHD
...\ADDER10B.VHD
...\ADDER32B.VHD
...\adder7b.vhd
...\cmp_state.ini
...\db
...\..\altsyncram_0sj2.tdf
...\..\altsyncram_5mp.tdf
...\..\altsyncram_6v51.tdf
...\..\altsyncram_hq21.tdf
...\..\dds.asm.qmsg
...\..\dds.cbx.xml
...\..\dds.cmp.cdb
...\..\dds.cmp.hdb
...\..\dds.cmp.kpt
...\..\dds.cmp.logdb
...\..\dds.cmp.rdb
...\..\dds.cmp.tdb
...\..\dds.cmp0.ddb
...\..\dds.dbp
...\..\dds.db_info
...\..\dds.eco.cdb
...\..\dds.eds_overflow
...\..\dds.fit.qmsg
...\..\dds.hier_info
...\..\dds.hif
...\..\dds.map.cdb
...\..\dds.map.hdb
...\..\dds.map.logdb
...\..\dds.map.qmsg
...\..\dds.pre_map.cdb
...\..\dds.pre_map.hdb
...\..\dds.psp
...\..\dds.pss
...\..\dds.rtlv.hdb
...\..\dds.rtlv_sg.cdb
...\..\dds.rtlv_sg_swap.cdb
...\..\dds.sgdiff.cdb
...\..\dds.sgdiff.hdb
...\..\dds.signalprobe.cdb
...\..\dds.sim.hdb
...\..\dds.sim.qmsg
...\..\dds.sim.rdb
...\..\dds.sim.vwf
...\..\dds.sld_design_entry.sci
...\..\dds.sld_design_entry_dsc.sci
...\..\dds.syn_hier_info
...\..\dds.tan.qmsg
...\..\dds_cmp.qrpt
...\..\dds_sim.qrpt
...\..\decode_ogi.tdf
...\..\wed.zsf
...\dds.asm.rpt
...\dds.cdf
...\dds.done
...\dds.fit.eqn
...\dds.fit.rpt
...\dds.fit.smsg
...\dds.fit.summary
...\dds.flow.rpt
...\dds.map.eqn
...\dds.map.rpt
...\dds.map.summary
...\dds.pin
...\dds.pof
...\dds.qpf
...\dds.qsf
...\dds.qws
...\dds.sim.rpt
...\dds.sof
...\dds.tan.rpt
...\dds.tan.summary
...\DDS.VHD
...\dds.vwf
...\dds_assignment_defaults.qdf
...\fsk_decode.vhd
...\LUT10X10.MIF
...\ps7.vhd
...\REG10B.VHD
...\REG32B.VHD
...\reg7b.vhd
...\sin7.mif
...\SIN_ROM.VHD