文件名称:ddsyixiang

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 1.64mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 刘**
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

dds数字移相信号发生器,功能齐全通过验证-dds digital shift Signal Generator, full-featured validated
(系统自动生成,下载前可以参看下载内容)

下载文件列表

dds数字移相信号发生器

.....................\ADDER10B.vhd

.....................\ADDER32B.vhd

.....................\ADDER32B.vhd.bak

.....................\db

.....................\..\altsyncram_dmi2.tdf

.....................\..\altsyncram_hmi2.tdf

.....................\..\altsyncram_imi2.tdf

.....................\..\altsyncram_u631.tdf

.....................\..\cmpr_fnh.tdf

.....................\..\cntr_78i.tdf

.....................\..\cntr_efh.tdf

.....................\..\cntr_fii.tdf

.....................\..\cntr_g9j.tdf

.....................\..\cntr_hek.tdf

.....................\..\cntr_hfh.tdf

.....................\..\cntr_ifh.tdf

.....................\..\DDS_VHDL.asm.qmsg

.....................\..\DDS_VHDL.cbx.xml

.....................\..\DDS_VHDL.cmp.bpm

.....................\..\DDS_VHDL.cmp.cdb

.....................\..\DDS_VHDL.cmp.ecobp

.....................\..\DDS_VHDL.cmp.hdb

.....................\..\DDS_VHDL.cmp.logdb

.....................\..\DDS_VHDL.cmp.rdb

.....................\..\DDS_VHDL.cmp.tdb

.....................\..\DDS_VHDL.cmp0.ddb

.....................\..\DDS_VHDL.cmp_bb.cdb

.....................\..\DDS_VHDL.cmp_bb.hdb

.....................\..\DDS_VHDL.cmp_bb.logdb

.....................\..\DDS_VHDL.cmp_bb.rcf

.....................\..\DDS_VHDL.dbp

.....................\..\DDS_VHDL.db_info

.....................\..\DDS_VHDL.ddsvh_8d88e121a32947c7c322e290b4eb49a51.cmp.atm

.....................\..\DDS_VHDL.ddsvh_8d88e121a32947c7c322e290b4eb49a51.map.atm

.....................\..\DDS_VHDL.eco.cdb

.....................\..\DDS_VHDL.fit.qmsg

.....................\..\DDS_VHDL.hier_info

.....................\..\DDS_VHDL.hif

.....................\..\DDS_VHDL.map.bpm

.....................\..\DDS_VHDL.map.cdb

.....................\..\DDS_VHDL.map.ecobp

.....................\..\DDS_VHDL.map.hdb

.....................\..\DDS_VHDL.map.logdb

.....................\..\DDS_VHDL.map.qmsg

.....................\..\DDS_VHDL.map_bb.cdb

.....................\..\DDS_VHDL.map_bb.hdb

.....................\..\DDS_VHDL.map_bb.logdb

.....................\..\DDS_VHDL.pre_map.cdb

.....................\..\DDS_VHDL.pre_map.hdb

.....................\..\DDS_VHDL.psp

.....................\..\DDS_VHDL.pss

.....................\..\DDS_VHDL.rtlv.hdb

.....................\..\DDS_VHDL.rtlv_sg.cdb

.....................\..\DDS_VHDL.rtlv_sg_swap.cdb

.....................\..\DDS_VHDL.sgdiff.cdb

.....................\..\DDS_VHDL.sgdiff.hdb

.....................\..\DDS_VHDL.signalprobe.cdb

.....................\..\DDS_VHDL.sldhu_30e344a040fd07e1533c49de5f2d67d1.cmp.atm

.....................\..\DDS_VHDL.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.atm

.....................\..\DDS_VHDL.sld_design_entry.sci

.....................\..\DDS_VHDL.sld_design_entry_dsc.sci

.....................\..\DDS_VHDL.syn_hier_info

.....................\..\DDS_VHDL.tan.qmsg

.....................\..\decode_ogi.tdf

.....................\..\prev_cmp_DDS_VHDL.asm.qmsg

.....................\..\prev_cmp_DDS_VHDL.fit.qmsg

.....................\..\prev_cmp_DDS_VHDL.map.qmsg

.....................\..\prev_cmp_DDS_VHDL.tan.qmsg

.....................\DDS_VHDL.asm.rpt

.....................\DDS_VHDL.bsf

.....................\DDS_VHDL.cdf

.....................\DDS_VHDL.done

.....................\DDS_VHDL.dpf

.....................\DDS_VHDL.fit.rpt

.....................\DDS_VHDL.fit.smsg

.....................\DDS_VHDL.fit.summary

.....................\DDS_VHDL.flow.rpt

.....................\DDS_VHDL.jdi

.....................\DDS_VHDL.map.rpt

.....................\DDS_VHDL.map.summary

.....................\DDS_VHDL.pin

.....................\DDS_VHDL.pof

.....................\DDS_VHDL.qpf

.....................\DDS_VHDL.qsf

.....................\DDS_VHDL.sof

.....................\DDS_VHDL.tan.rpt

.....................\DDS_VHDL.tan.summary

.....................\DDS_VHDL.vhd

.....................\DDS_VHDL.vhd.bak

.....................\greybox_tmp

.....................\LUT10X10.MIF

.....................\prev_cmp_DDS_VHDL.qmsg

.....................\REG10B.vhd

.....................\REG32B.vhd

..........

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